公开(公告)号：US08330596B2

公开(公告)日：2012-12-11

申请号：US12155457

申请日：2008-06-04

申请人： Takeshi Tanaka ,  Shunzo Yamashita ,  Kiyoshi Aiki

发明人： Takeshi Tanaka ,  Shunzo Yamashita ,  Kiyoshi Aiki

IPC分类号： G08B1/08

CPC分类号： A61B5/0002 ,  A61B5/02438 ,  A61B5/11 ,  A61B5/7232 ,  A61B2560/045 ,  A61B2562/0219 ,  H04W84/18

摘要： Provided is a sensor node including: a sensor for measuring biological information; a CPU for acquiring data by driving the sensor; a wireless communication unit for transmitting the data acquired by the CPU; a battery for supplying the control unit, the wireless communication unit, and the sensor with electric power; a RAM for storing the data; a compression unit for compressing the data stored in the RAM when the wireless communication unit cannot carry out the transmission; and a flash memory for storing the compressed data, thereby storing as much sensing data as possible on the sensor node, which is limited in resources, and preventing loss of the sensing data.

摘要翻译： 提供了一种传感器节点，包括：用于测量生物信息的传感器; 用于通过驱动传感器来获取数据的CPU; 用于发送由CPU获取的数据的无线通信单元; 用于向控制单元，无线通信单元和传感器供电的电池; 用于存储数据的RAM; 压缩单元，用于在无线通信单元不能进行发送时压缩存储在RAM中的数据; 以及用于存储压缩数据的闪速存储器，从而在传感器节点上存储尽可能多的感测数据，其在资源上受到限制，并且防止感测数据的丢失。

公开(公告)号：US20060092907A1

公开(公告)日：2006-05-04

申请号：US11072363

申请日：2005-03-07

申请人： Isao Shimokawa ,  Shunzo Yamashita

发明人： Isao Shimokawa ,  Shunzo Yamashita

IPC分类号： H04B7/212 ,  H04Q7/24

CPC分类号： H04W72/10 ,  H04L1/1867 ,  H04W52/0235 ,  H04W74/0808 ,  H04W76/27

摘要： A radio communication system suitable for a sensor net system is provided. In a TDMA method, one slot is divided into four periods. Even when a majority of sensor nodes simultaneously perform access, they can settle in a steady state in high speed corresponding to the transition response of the system. Even when sleep time intervals of the sensor nodes are changed according to the priority thereof and the transmission intervals of the sensor nodes are not constant, the TDMA method control can be performed. Moreover, even when the transmission intervals of the sensor nodes are not constant, the original system performance is not deteriorated.

摘要翻译： 提供了适用于传感器网络系统的无线电通信系统。 在TDMA方法中，一个时隙被分成四个周期。 即使大多数传感器节点同时执行访问，它们可以以对应于系统的转换响应的高速度稳定地稳定。 即使传感器节点的睡眠时间间隔根据其优先级而改变，并且传感器节点的传输间隔不是恒定的，所以可以执行TDMA方法控制。 此外，即使当传感器节点的传输间隔不恒定时，原始系统性能也不会恶化。

公开(公告)号：US20060076934A1

公开(公告)日：2006-04-13

申请号：US11072490

申请日：2005-03-07

申请人： Yuji Ogata ,  Shunzo Yamashita ,  Takanori Shimura ,  Kiyoshi Aiki

发明人： Yuji Ogata ,  Shunzo Yamashita ,  Takanori Shimura ,  Kiyoshi Aiki

IPC分类号： H02J7/00

CPC分类号： H02J7/0031

摘要： In a sensor node SN driven by a secondary battery, a charge/discharge control circuit can be realized and an unnecessary circuit in the sensor node can be eliminated for its miniaturization. The charge/discharge control circuit and the sensor node have a comparator for monitoring a battery voltage, a control circuit for converting an output of the comparator into an interrupt signal, a micro controller for performing charge/discharge control only when detecting the interrupt signal, and a switch turned ON or OFF under control of the micro controller. When the battery voltage is not lower than a first predetermined voltage, the switch is turned OFF to thereby stop charging operation. When the battery voltage is not higher than a second predetermined voltage, the switch is turned OFF to stop discharging operation. A circuit necessary in a charge mode is provided in a charger side.

摘要翻译： 在由二次电池驱动的传感器节点SN中，可以实现充放电控制电路，并且可以消除传感器节点中的不必要的电路以使其小型化。 充放电控制电路和传感器节点具有用于监视电池电压的比较器，用于将比较器的输出转换为中断信号的控制电路，仅在检测到中断信号时执行充放电控制的微控制器， 并且在微控制器的控制下开关被接通或断开。 当电池电压不低于第一预定电压时，开关断开，从而停止充电操作。 当电池电压不高于第二预定电压时，开关断开以停止放电操作。 在充电器侧提供充电模式所需的电路。

公开(公告)号：US06651223B2

公开(公告)日：2003-11-18

申请号：US10287599

申请日：2002-11-05

申请人： Shunzo Yamashita ,  Kazuo Yano ,  Naoki Kato

发明人： Shunzo Yamashita ,  Kazuo Yano ,  Naoki Kato

IPC分类号： G06F1750

CPC分类号： G06F17/505

摘要： A method, system, and library for generating high-speed logic circuits with reduced path depths even in cases when a critical path diverges into a plurality of paths that eventually converge. By replacing the gates of a logic circuit by selectors with two inputs and one output, a selector-based circuit is generated where a local circuit between the path divergence node and convergence node is detected. The stages of the critical path are reduced by replacing the local circuit by a logically equivalent selector with two inputs and one output; wherein one input of the selector is controlled by a circuit formed by inputting a logical value of “0” to the divergence node from which the local circuit is developed and a second input of the selector is controlled by a circuit formed by inputting a logical value of “1” to the divergence node.

公开(公告)号：US06505322B2

公开(公告)日：2003-01-07

申请号：US09904661

申请日：2001-07-16

申请人： Shunzo Yamashita ,  Kazuo Yano ,  Naoki Kato

发明人： Shunzo Yamashita ,  Kazuo Yano ,  Naoki Kato

IPC分类号： G06F1750

CPC分类号： G06F17/505

摘要： A method, system, and library for generating high-speed logic circuits with reduced path depths even in cases when a critical path diverges into a plurality of paths that eventually converge. By replacing the gates of a logic circuit by selectors with two inputs and one output, a selector-based circuit is generated where a local circuit between the path divergence node and convergence node is detected. The stages of the critical path are reduced by replacing the local circuit by a logically equivalent selector with two inputs and one output; wherein one input of the selector is controlled by a circuit formed by inputting a logical value of “0” to the divergence node from which the local circuit is developed and a second input of the selector is controlled by a circuit formed by inputting a logical value of “1” to the divergence node.

公开(公告)号：US06313665B1

公开(公告)日：2001-11-06

申请号：US09402648

申请日：2000-02-03

申请人： Yasuhiko Sasaki ,  Kunihito Rikino ,  Kazuo Yano ,  Shunzo Yamashita

发明人： Yasuhiko Sasaki ,  Kunihito Rikino ,  Kazuo Yano ,  Shunzo Yamashita

IPC分类号： H01L2710

CPC分类号： H03K19/1737 ,  H01L27/0207 ,  H01L27/11898

摘要： The I/O terminal positions of a pass transistor logic circuit cell are distributed in the cell, an output amplifier is provided on the end part of the cell, the pass transistor circuit is arranged in the direction in which a potential supply line extends, a signal polarity inverting circuit is laid out in the cell and the arrangement of wells is different from the arrangement of a conventional CMOS logic circuit.

摘要翻译： 传输晶体管逻辑电路单元的I / O端子位置分布在单元中，输出放大器设置在单元的端部，传输晶体管电路沿电位线延伸的方向排列， 信号极性反转电路布置在单元中，并且阱的布置不同于传统CMOS逻辑电路的布置。

公开(公告)号：US6049232A

公开(公告)日：2000-04-11

申请号：US225291

申请日：1999-01-05

申请人： Yasuhiko Sasaki ,  Kazuo Yano ,  Shunzo Yamashita ,  Koichi Seki

发明人： Yasuhiko Sasaki ,  Kazuo Yano ,  Shunzo Yamashita ,  Koichi Seki

IPC分类号： G06F17/50 ,  H03K19/173 ,  H03K19/0948

CPC分类号： H03K19/1736 ,  G06F17/505 ,  H03K19/1737

摘要： For the relation between the first and second pass-transistor circuits (PT1, PT2), the output signal of the preceding-stage is supplied to the gate of the succeeding-stage, and for the relation between the second and third pass-transistor circuits (PT2, PT3), the output signal of the preceding-stage is supplied to the source-drain path of the succeeding-stage. The first pass-transistor circuit (PT1) receives on its first input node (In1) and second input node (In2) the first input signal and the second input signal that are logically independent from each other. This logic circuit requires a smaller number of transistors and is capable of reducing the power consumption and delay and accomplishing an intricate logic function.

公开(公告)号：US5712792A

公开(公告)日：1998-01-27

申请号：US633486

申请日：1996-04-17

申请人： Shunzo Yamashita ,  Kazuo Yano ,  Yasuhiko Sasaki ,  Koichi Seki

发明人： Shunzo Yamashita ,  Kazuo Yano ,  Yasuhiko Sasaki ,  Koichi Seki

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： In order to effectively explore a binary decision diagram for synthesizing a logic circuit, a tentative circuit comprised of AND gates and OR gates is synthesized from a logic function. The number of gates in this circuit to which two input variables are simultaneously associated are counted and used as correlation between the two input variables. A correlation matrix for correlation among all of the input variables is generated. The input variables are sequentially grouped from a set of input variables with strongest correlation in the correlation matrix: These groups are registered into a correlation tree, and an intergroup correlation tree is produced. These groups are sequentially selected from a group with the least correlation, and the intragroup order of the selected group is changed from one to another. A binary decision diagram is explored which satisfies the most appropriate condition in that group (such as the minimum number of nodes, the minimum delay, and the minimum area). The above processes repeated for all groups. Each node of the binary decision diagram thus obtained is substituted by a selector and each selector circuit is substituted by a circuit of a transistor level.

摘要翻译： 为了有效地研究用于合成逻辑电路的二进制判定图，从逻辑功能合成了由与门和或门组成的暂定电路。 两个输入变量同时关联的该电路中的门数被计数并用作两个输入变量之间的相关。 生成所有输入变量之间相关的相关矩阵。 输入变量从相关矩阵中具有最强相关性的一组输入变量顺序分组：将这些组注册到相关树中，并产生一个组间相关树。 从具有最小相关性的组中顺序地选择这些组，并且所选择的组的组内顺序从一个改变为另一组。 探讨了满足该组中最合适条件（如最小节点数，最小延迟和最小面积）的二进制决策图。 上述过程对所有组重复。 由此获得的二进制判定图的每个节点由选择器代替，并且每个选择器电路被晶体管电平的电路代替。

公开(公告)号：US07289034B2

公开(公告)日：2007-10-30

申请号：US11072402

申请日：2005-03-07

申请人： Yoshihiro Wakisaka ,  Shunzo Yamashita ,  Toshiyuki Odaka ,  Norio Ohkubo

发明人： Yoshihiro Wakisaka ,  Shunzo Yamashita ,  Toshiyuki Odaka ,  Norio Ohkubo

IPC分类号： G08B21/00

CPC分类号： G01D3/08 ,  Y10T307/74

摘要： A radio terminal device realizing reduced power consumption and prompt detection of detection object by using a first sensor and a second sensor whose ON/OFF states are opposite and whose operations are synchronized. When the first sensor detects a detection object, the first output voltage level is changed. When a processor detects the change of the output voltage level as an interrupt signal, the drive voltage level of the first sensor is switched to low and the drive voltage level of the second sensor is switched to high. Moreover, when the second sensor detects a detection object, the output voltage level of the second sensor is changed. When the processor detects the change of the output voltage level as an interrupt signal, the drive voltage level of the second sensor is switched to low and the drive voltage level of the first circuit is switched to high.

摘要翻译： 一种无线终端装置，其通过使用第一传感器和ON / OFF状态相反并且其操作同步的第二传感器来实现降低的功耗并迅速检测检测对象。 当第一传感器检测到检测对象时，第一输出电压电平发生变化。 当处理器检测到作为中断信号的输出电压电平的变化时，第一传感器的驱动电压电平被切换到低电平，并且第二传感器的驱动电压电平被切换到高电平。 此外，当第二传感器检测到检测对象时，第二传感器的输出电压电平发生变化。 当处理器检测到输出电压电平的变化作为中断信号时，第二传感器的驱动电压电平被切换到低电平，并且第一电路的驱动电压电平被切换到高电平。

公开(公告)号：US07187961B2

公开(公告)日：2007-03-06

申请号：US10457498

申请日：2003-06-10

申请人： Shunzo Yamashita ,  Kei Suzuki ,  Toshiyuki Aritsuka ,  Masayuki Miyazaki ,  Sadaki Nakano

发明人： Shunzo Yamashita ,  Kei Suzuki ,  Toshiyuki Aritsuka ,  Masayuki Miyazaki ,  Sadaki Nakano

IPC分类号： A61B5/00

CPC分类号： A61B5/0002 ,  A61B5/02055 ,  A61B5/02427 ,  A61B5/0531 ,  A61B5/11 ,  A61B5/7232 ,  A61B2560/0209 ,  A61B2560/0412 ,  A61B2562/0219 ,  A61B2562/028 ,  A61B2562/08 ,  G01D9/005 ,  G01K7/01 ,  G01K2215/00 ,  G01P15/125 ,  G01P2015/0814 ,  H01L35/32 ,  H01L2924/0002 ,  Y10S128/903 ,  H01L2924/00

摘要： A semiconductor device is employable for a compact and light-weight sensor system that is free of the need for battery replacement. The semiconductor device has a sensor chip (SCHIP1) comprising sensors (TD1, AS1, PD1, GS1), an A/D conversion circuit (AD1), a microprocessor (CPU1), a memory (MEM1), a transmission circuit (RF1), and a power generation circuit (CM1). The sensors, the A/D conversion circuit, the microprocessor, the memory, and the transmission circuit are formed on one side (SIDE1) of a substrate, while the power generation unit is formed on the other side (SIDE2) of the substrate.

摘要翻译： 半导体器件可用于紧凑且轻量的传感器系统，其不需要更换电池。 半导体器件具有传感器芯片（SCHIP1），包括传感器（TD1，AS1，PD1，GS1），A / D转换电路（AD 1），微处理器（CPU 1），存储器 ），发送电路（RF 1）和发电电路（CM 1）。 传感器，A / D转换电路，微处理器，存储器和传输电路形成在衬底的一侧（SIDE 1）上，而发电单元形成在衬底的另一侧（SIDE 2）上 基质。