公开(公告)号：US11864468B2

公开(公告)日：2024-01-02

申请号：US17348776

申请日：2021-06-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Si-Han Tsai ,  Dong-Ming Wu ,  Chen-Yi Weng ,  Ching-Hua Hsu ,  Ju-Chun Fan ,  Yi-Yu Lin ,  Che-Wei Chang ,  Po-Kai Hsu ,  Jing-Yin Jhang

IPC: G11C16/04 ,  H10N50/10 ,  H01F10/32 ,  G11C11/16 ,  H10B61/00 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10N50/10 ,  G11C11/161 ,  H01F10/3254 ,  H10B61/00 ,  H10N50/80 ,  H10N50/85

Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.

公开(公告)号：US20230232638A1

公开(公告)日：2023-07-20

申请号：US17673760

申请日：2022-02-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Ju-Chun Fan ,  Ching-Hua Hsu ,  Chun-Hao Wang ,  Yi-Yu Lin ,  Dong-Ming Wu ,  Po-Kai Hsu

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  G11C5/02 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L27/226 ,  H01L43/02 ,  H01L43/08 ,  G11C5/02 ,  H01L23/5226 ,  H01L23/5283

Abstract: Abstract of Disclosure A memory array includes at least one strap region, at least two sub-arrays, a plurality of staggered, dummy magnetic storage elements, and a plurality of bit line structures. The strap region includes a plurality of source line straps and a plurality of word line straps. The two sub-arrays include a plurality of staggered, active magnetic storage elements. The two sub -arrays are separated by the strap region. The staggered, dummy magnetic storage elements are disposed within the strap region. The bit line structures are disposed in the two sub-arrays, and each of the bit line structures is disposed above and directly connected with at least one of the staggered, active magnetic storage elements.

公开(公告)号：US20220367791A1

公开(公告)日：2022-11-17

申请号：US17348776

申请日：2021-06-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Si-Han Tsai ,  Dong-Ming Wu ,  Chen-Yi Weng ,  Ching-Hua Hsu ,  Ju-Chun Fan ,  Yi-Yu Lin ,  Che-Wei Chang ,  Po-Kai Hsu ,  Jing-Yin Jhang

IPC: H01L43/08 ,  H01L43/02 ,  H01L43/10 ,  G11C11/16 ,  H01L27/22 ,  H01F10/32

Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.

公开(公告)号：US20220310902A1

公开(公告)日：2022-09-29

申请号：US17242322

申请日：2021-04-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Ching-Hua Hsu ,  Si-Han Tsai ,  Shun-Yu Huang ,  Chen-Yi Weng ,  Ju-Chun Fan ,  Che-Wei Chang ,  Yi-Yu Lin ,  Po-Kai Hsu ,  Jing-Yin Jhang ,  Ya-Jyuan Hung

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12

Abstract: A magnetoresistive random access memory (MRAM) structure, including a substrate and multiple MRAM cells on the substrate, wherein the MRAM cells are arranged in a memory region adjacent to a logic region. An ultra low-k (ULK) layer covers the MRAM cells, wherein the surface portion of ultra low-k layer is doped with fluorine, and dents are formed on the surface of ultra low-k layer at the boundaries between the memory region and the logic region.

公开(公告)号：US20220115584A1

公开(公告)日：2022-04-14

申请号：US17088531

申请日：2020-11-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Ju-Chun Fan ,  Ching-Hua Hsu ,  Yi-Yu Lin ,  Hung-Yueh Chen

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a first inter-metal dielectric (IMD) layer on a substrate and a metal interconnection in the first IMD layer, forming a magnetic tunneling junction (MTJ) and a top electrode on the metal interconnection, forming a spacer adjacent to the MTJ and the top electrode, forming a second IMD layer around the spacer, forming a cap layer on the top electrode, the spacer, and the second IMD layer, and then patterning the cap layer to form a protective cap on the top electrode and the spacer.