公开(公告)号：US09653558B2

公开(公告)日：2017-05-16

申请号：US14739702

申请日：2015-06-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Kai-Kuen Chang ,  Kun-Huang Yu

IPC: H01L27/088 ,  H01L29/40 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L29/404 ,  H01L21/762 ,  H01L23/485 ,  H01L23/522 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a source region, a drain region, a gate, and a dummy contact. The source region and the drain region are formed in the substrate. The gate is formed on the substrate and between the source region and the drain region. The dummy contact includes a plurality of dummy plugs formed on the substrate, wherein the dummy plugs have depths decreasing towards the drain region.

公开(公告)号：US09349818B2

公开(公告)日：2016-05-24

申请号：US14519153

申请日：2014-10-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Huang Yu ,  Shih-Yin Hsiao

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/66545 ,  H01L21/76895 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/401 ,  H01L29/402 ,  H01L29/4238 ,  H01L29/66568 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7835

Abstract: A MOS transistor device includes a substrate including a gate formed thereon, and a spacer being formed on a sidewall of the gate; a source region and a drain region formed in the substrate; and at least a first dummy contact formed above the substrate on a drain side of the gate. More important, the first dummy contact is formed apart from a surface of the substrate.

Abstract translation: MOS晶体管器件包括其上形成有栅极的衬底和形成在栅极的侧壁上的间隔物; 形成在所述基板中的源极区域和漏极区域; 以及形成在栅极的漏极侧的衬底上方的至少第一虚拟接触。 更重要的是，第一虚拟接触件与衬底的表面分开形成。

公开(公告)号：US09236471B2

公开(公告)日：2016-01-12

申请号：US14253365

申请日：2014-04-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chiu-Te Lee ,  Ke-Feng Lin ,  Shu-Wen Lin ,  Kun-Huang Yu ,  Chih-Chung Wang ,  Te-Yuan Wu

IPC: H01L29/76 ,  H01L29/78 ,  H01L29/40 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/407

Abstract: A semiconductor structure comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate; a first well having the first conductive type and a second well having the second conductive type both formed in the deep well and the second well spaced apart from the first well; a gate electrode formed on the substrate and disposed between the first and second wells; an isolation extending down from the surface of the substrate and disposed between the gate electrode and the second well; a conductive plug including a first portion and a second portion electrically connected to each other, and the first portion electrically connected to the gate electrode, and the second portion penetrating into the isolation. The bottom surface of the second portion of the conductive plug is covered by the isolation.

Abstract translation: 半导体结构包括具有第一导电类型的衬底; 在衬底中形成有第二导电类型的深阱; 具有第一导电类型的第一阱和具有第二导电类型的第二阱都形成在深阱中并且第二阱与第一阱间隔开; 栅电极，形成在所述基板上并且设置在所述第一阱和所述第二阱之间; 从衬底的表面向下延伸并且设置在栅电极和第二阱之间的隔离件; 导电插头，其包括彼此电连接的第一部分和第二部分，并且所述第一部分电连接到所述栅电极，并且所述第二部分穿透所述隔离。 导电插头的第二部分的底表面被隔离层覆盖。

公开(公告)号：US08896057B1

公开(公告)日：2014-11-25

申请号：US13893635

申请日：2013-05-14

Applicant: United Microelectronics Corp.

Inventor： Kun-Huang Yu

IPC: H01L29/76 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/404 ,  H01L29/0649 ,  H01L29/407 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/7816

Abstract: A semiconductor structure comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate and extending down from a surface of the substrate; a first well and a second well respectively having the first and second conductive types formed in the deep well, and extending down from the surface of the substrate; a gate electrode formed on the substrate and disposed between the first and second wells; an isolation extending down from the surface of the substrate and disposed between the gate electrode and the second well; a conductive plug including a first portion and a second portion electrically connected to each other, and the first portion electrically connected to the gate electrode, and the second portion comprising at least two fingers penetrating into the isolation, and the fingers spaced apart and electrically connected to each other.

Abstract translation: 半导体结构包括具有第一导电类型的衬底; 具有形成在所述基板中并从所述基板的表面向下延伸的第二导电类型的深阱; 第一阱和第二阱分别具有形成在深阱中的第一和第二导电类型，并从衬底的表面向下延伸; 栅电极，形成在所述基板上并且设置在所述第一阱和所述第二阱之间; 从衬底的表面向下延伸并且设置在栅电极和第二阱之间的隔离件; 导电插头，其包括彼此电连接的第一部分和第二部分，并且所述第一部分电连接到所述栅电极，并且所述第二部分包括穿透到所述隔离物中的至少两个手指，并且所述手指间隔开并电连接 对彼此。