公开(公告)号：US20170125583A1

公开(公告)日：2017-05-04

申请号：US14930596

申请日：2015-11-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Kun-Huang Yu

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/423 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1087 ,  H01L29/42364 ,  H01L29/7836

Abstract: A high voltage transistor includes a substrate, a well which is disposed within the substrate, a gate disposed on the well, a gate dielectric layer disposed between the well and the gate, two drift regions respectively disposed in the well at two sides of the gate, two source/drain regions respectively disposed within each drift region, wherein a width of the gate dielectric layer is smaller than a width of the source/drain region, and two isolation elements respectively disposed within each drift region

公开(公告)号：US09466694B2

公开(公告)日：2016-10-11

申请号：US15132256

申请日：2016-04-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Huang Yu ,  Shih-Yin Hsiao

IPC: H01L29/78 ,  H01L21/768 ,  H01L29/66 ,  H01L29/40 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/66545 ,  H01L21/76895 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/401 ,  H01L29/402 ,  H01L29/4238 ,  H01L29/66568 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7835

Abstract: A method for manufacturing a MOS transistor device includes following steps. A substrate including at least an isolation structure formed therein is provided. Next, a MOS transistor device is formed on the substrate, the MOS transistor device includes a gate, a source region, a drain region and a spacer. After forming the MOS transistor device, at least a first dummy contact is formed on a drain side of the gate and a gate contact is formed to be electrically connected to the gate. The first dummy contact is spaced apart from a surface of the substrate and electrically connected to the gate contact.

Abstract translation: 一种用于制造MOS晶体管器件的方法包括以下步骤。 提供了至少包括形成在其中的隔离结构的基板。 接下来，在基板上形成MOS晶体管器件，MOS晶体管器件包括栅极，源极区域，漏极区域和间隔物。 在形成MOS晶体管器件之后，在栅极的漏极侧形成至少第一虚拟触点，并且形成与栅极电连接的栅极接触。 第一虚拟触点与衬底的表面间隔开并且电连接到栅极触点。

公开(公告)号：US09196695B2

公开(公告)日：2015-11-24

申请号：US14273538

申请日：2014-05-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Huang Yu ,  Shih-Yin Hsiao ,  Wen-Fang Lee ,  Shu-Wen Lin ,  Kuan-Chuan Chen

IPC: H01L29/76 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/08 ,  H01L21/266 ,  H01L21/28

CPC classification number: H01L29/42368 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/28026 ,  H01L21/28158 ,  H01L21/2822 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/401 ,  H01L29/6659 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7834

Abstract: The present invention provides a high-voltage metal-oxide-semiconductor (HVMOS) transistor comprising a substrate, a gate dielectric layer, a gate electrode and a source and drain region. The gate dielectric layer is disposed on the substrate and includes a protruded portion and a recessed portion, wherein the protruded portion is disposed adjacent to two sides of the recessed portion and has a thickness greater than a thickness of the recessed portion. The gate electrode is disposed on the gate dielectric layer. Thus, the protruded portion of the gate dielectric layer can maintain a higher breakdown voltage, thereby keeping the current from leaking through the gate.

Abstract translation: 本发明提供一种高压金属氧化物半导体（HVMOS）晶体管，其包括衬底，栅极电介质层，栅极电极和源极和漏极区域。 栅介质层设置在基板上，并且包括突出部分和凹陷部分，其中突出部分邻近凹部的两侧设置，并且具有大于凹部的厚度的厚度。 栅电极设置在栅介质层上。 因此，栅极电介质层的突出部分可以保持更高的击穿电压，从而保持电流不通过栅极泄漏。

公开(公告)号：US10340349B2

公开(公告)日：2019-07-02

申请号：US15799692

申请日：2017-10-31

Applicant: United Microelectronics Corp.

Inventor： Kun-Huang Yu ,  Shih-Yin Hsiao

IPC: H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L49/02 ,  H01L29/423 ,  H01L29/788 ,  H01L27/11521

Abstract: A method of forming a semiconductor structure is disclosed. A substrate having a first area and a second area is provided, wherein a first surface of the first area is lower than a second surface of the second area. A first insulating layer, a first gate, a first dielectric layer and a first dummy gate are sequentially formed on the first surface of the first area. A second dielectric layer and a second dummy gate are formed on the second surface of the second area. An inter-layer dielectric layer is formed around the first gate, the first dummy gate and the second dummy gate. The first dummy gate and the second dummy gate are removed, so as to form a first trench and a second trench in the inter-layer dielectric layer. A second gate and a third gate are filled respectively in the first trench and the second trench.

公开(公告)号：US20180069089A1

公开(公告)日：2018-03-08

申请号：US15799692

申请日：2017-10-31

Applicant: United Microelectronics Corp.

Inventor： Kun-Huang Yu ,  Shih-Yin Hsiao

IPC: H01L29/423 ,  H01L29/788 ,  H01L29/66 ,  H01L21/28 ,  H01L29/49

CPC classification number: H01L29/42328 ,  H01L21/28273 ,  H01L27/11521 ,  H01L28/00 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/788

Abstract: A method of forming a semiconductor structure is disclosed. A substrate having a first area and a second area is provided, wherein a first surface of the first area is lower than a second surface of the second area. A first insulating layer, a first gate, a first dielectric layer and a first dummy gate are sequentially formed on the first surface of the first area. A second dielectric layer and a second dummy gate are formed on the second surface of the second area. An inter-layer dielectric layer is formed around the first gate, the first dummy gate and the second dummy gate. The first dummy gate and the second dummy gate are removed, so as to form a first trench and a second trench in the inter-layer dielectric layer. A second gate and a third gate are filled respectively in the first trench and the second trench.

公开(公告)号：US20170062444A1

公开(公告)日：2017-03-02

申请号：US14863177

申请日：2015-09-23

Applicant: United Microelectronics Corp.

Inventor： Kun-Huang Yu ,  Shih-Yin Hsiao

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L21/28273 ,  H01L27/11536 ,  H01L27/11539 ,  H01L29/42336

Abstract: Provided is a memory device including a first gate, a second gate and an inter-gate dielectric layer. The first gate is buried in a substrate. The second gate includes metal and is disposed on the substrate. The inter-gate dielectric layer is disposed between the first and second gates. A method of forming a memory device is further provided.

Abstract translation: 提供了包括第一栅极，第二栅极和栅极间电介质层的存储器件。 第一个栅极被埋在基板中。 第二栅极包括金属并且设置在基板上。 栅极间介电层设置在第一和第二栅极之间。 还提供了形成存储器件的方法。

公开(公告)号：US09461133B1

公开(公告)日：2016-10-04

申请号：US14748255

申请日：2015-06-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Kun-Huang Yu

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/423 ,  H01L29/66 ,  H01L21/266 ,  H01L29/10

CPC classification number: H01L29/4238 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/28105 ,  H01L21/28114 ,  H01L29/1095 ,  H01L29/42376 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/66704 ,  H01L29/7816 ,  H01L29/7835

Abstract: A high voltage metal-oxide-semiconductor transistor device having stepped gate structure and a manufacturing method thereof are provided. The manufacturing method includes following steps. A gate structure is formed on a semiconductor substrate. The semiconductor substrate includes a first region and a second region disposed on a side of a first part of the gate structure and a side of a second part of the gate structure respectively. A patterned mask layer is formed on the semiconductor substrate and the gate structure. The patterned mask layer covers the first region and the first part. The second part is uncovered by the patterned mask layer. An implantation process is performed to form a drift region in the second region. An etching process is performed to remove a part of the second part uncovered by the patterned mask layer. A thickness of the second part is less than that of the first part after the etching process.

Abstract translation: 本发明提供一种具有台阶门结构的高电压金属氧化物半导体晶体管器件及其制造方法。 制造方法包括以下步骤。 栅极结构形成在半导体衬底上。 半导体衬底包括分别设置在栅极结构的第一部分的侧面上的第一区域和第二区域以及栅极结构的第二部分的一侧。 在半导体衬底和栅极结构上形成图案化掩模层。 图案化掩模层覆盖第一区域和第一部分。 第二部分被图案化掩模层覆盖。 执行注入处理以在第二区域中形成漂移区域。 执行蚀刻处理以去除未被图案化掩模层覆盖的第二部分的一部分。 在蚀刻处理之后，第二部分的厚度小于第一部分的厚度。

公开(公告)号：US10373837B2

公开(公告)日：2019-08-06

申请号：US15705014

申请日：2017-09-14

Applicant: United Microelectronics Corp.

Inventor： Kun-Huang Yu ,  Shih-Yin Hsiao

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/423 ,  H01L27/11536 ,  H01L27/11539

Abstract: Provided is a memory device including a first gate, a second gate and an inter-gate dielectric layer. The first gate is buried in a substrate. The second gate includes metal and is disposed on the substrate. The inter-gate dielectric layer is disposed between the first and second gates. The inter-gate dielectric layer comprises a high-k layer having a dielectric constant of greater than about 10.

公开(公告)号：US20170098696A1

公开(公告)日：2017-04-06

申请号：US14937514

申请日：2015-11-10

Applicant: United Microelectronics Corp.

Inventor： Kun-Huang Yu ,  Shih-Yin Hsiao

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/788 ,  H01L21/28 ,  H01L27/115 ,  H01L29/66

CPC classification number: H01L29/42328 ,  H01L27/11521 ,  H01L28/00 ,  H01L29/40114 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/788

Abstract: Provided is a semiconductor structure including a substrate, a first gate, a second gate, a third gate and an inter-gate dielectric layer. The substrate has a first area and a second area, and the first surface of the first area is lower than the second surface of the second area. The first gate is disposed on the first surface of the first area. The second gate includes metal and is disposed on the first gate. The inter-gate dielectric layer is disposed between the first and second gates. The third gate includes metal and is disposed on the second surface of the second area. A method of foaming a semiconductor structure is further provided.

公开(公告)号：US09484422B2

公开(公告)日：2016-11-01

申请号：US14882462

申请日：2015-10-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Huang Yu ,  Shih-Yin Hsiao ,  Wen-Fang Lee ,  Shu-Wen Lin ,  Kuan-Chuan Chen

IPC: H01L29/76 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/08 ,  H01L21/266 ,  H01L21/28 ,  H01L21/265

CPC classification number: H01L29/42368 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/28026 ,  H01L21/28158 ,  H01L21/2822 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/401 ,  H01L29/6659 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7834

Abstract: The present invention provides a high-voltage metal-oxide-semiconductor (HVMOS) transistor comprising a substrate, a gate dielectric layer, a gate electrode and a source and drain region. The gate dielectric layer is disposed on the substrate and includes a protruded portion and a recessed portion, wherein the protruded portion is disposed adjacent to two sides of the recessed portion and has a thickness greater than a thickness of the recessed portion. The gate electrode is disposed on the gate dielectric layer. Thus, the protruded portion of the gate dielectric layer can maintain a higher breakdown voltage, thereby keeping the current from leaking through the gate.

Abstract translation: 本发明提供一种高压金属氧化物半导体（HVMOS）晶体管，其包括衬底，栅极电介质层，栅极电极和源极和漏极区域。 栅介质层设置在基板上，并且包括突出部分和凹陷部分，其中突出部分邻近凹部的两侧设置，并且具有大于凹部的厚度的厚度。 栅电极设置在栅介质层上。 因此，栅极电介质层的突出部分可以保持更高的击穿电压，从而保持电流不通过栅极泄漏。