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    METHOD OF FORMING SEMICONDUCTOR DEVICE
    24.
    发明公开
    METHOD OF FORMING SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240074329A1

    公开(公告)日：2024-02-29

    申请号：US18505074

    申请日：2023-11-08

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Kuo-Hsing Lee ,  Chun-Hsien Lin ,  Sheng-Yuan Hsueh

    IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/85

    CPC classification number: H10N50/80 ,  H10B61/20 ,  H10B61/22 ,  H10N50/01 ,  H10N50/85

    Abstract: The present invention provides a semiconductor device and a method of forming the same, and the semiconductor device includes a substrate, a first interconnect layer and a second interconnect layer. The first interconnect layer is disposed on the substrate, and the first interconnect layer includes a first dielectric layer around a plurality of first magnetic tunneling junction (MTJ) structures. The second interconnect layer is disposed on the first interconnect layer, and the second interconnect layer includes a second dielectric layer around a plurality of second MTJ structures, wherein, the second MTJ structures and the first MTJ structures are alternately arranged along a direction. The semiconductor device may obtain a reduced size of each bit cell under a permissible process window, so as to improve the integration of components.

    ONE-TIME PROGRAMMABLE MEMORY STRUCTURE
    26.
    发明申请
    ONE-TIME PROGRAMMABLE MEMORY STRUCTURE 有权

    公开(公告)号：US20220336479A1

    公开(公告)日：2022-10-20

    申请号：US17323863

    申请日：2021-05-18

    Applicant: United Microelectronics Corp.

    Inventor： Kuo-Hsing Lee ,  Chi-Horn Pai ,  Chang Chien Wong ,  Sheng-Yuan Hsueh ,  Ching Hsiang Tseng ,  Shih-Chieh Hsu

    IPC: H01L27/112

    Abstract: A one-time programmable memory structure including a substrate, a transistor, a capacitor, and an interconnect structure is provided. The transistor is located on the substrate. The capacitor includes a first electrode, a second electrode, and an insulating layer. The first electrode is disposed above the substrate. The second electrode is disposed on the first electrode. The first electrode is located between the second electrode and the substrate. The insulating layer is disposed between the first electrode and the second electrode. The interconnect structure is electrically connected between the transistor and the first electrode of the capacitor. The interconnect structure is electrically connected to the first electrode at a top surface of the first electrode.

    Embedded MRAM structure and method of fabricating the same
    28.
    发明授权
    Embedded MRAM structure and method of fabricating the same 有权

    公开(公告)号：US10985211B1

    公开(公告)日：2021-04-20

    申请号：US16699758

    申请日：2019-12-02

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Ting-Hsiang Huang

    IPC: H01L27/22 ,  H01L43/12 ,  H01L23/538 ,  H01L29/417

    Abstract: An embedded MRAM structure includes a substrate divided into a memory cell region and a logic device region. An active area is disposed in the memory cell region. A word line is disposed on the substrate and crosses the active area. A source plug is disposed in the active area and at one side of the word line. A drain plug is disposed in the in the active area and at another side of the word line. When viewing from a direction perpendicular to the top surface of the substrate and taking the word line as a symmetric axis, the source plug is a mirror image of the drain plug.

    Semiconductor device
    30.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US10777508B2

    公开(公告)日：2020-09-15

    申请号：US15347757

    申请日：2016-11-09

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chih-Kai Kang ,  Sheng-Yuan Hsueh ,  Yi-Chung Sheng ,  Kuo-Yu Liao ,  Shu-Hung Yu ,  Hung-Hsu Lin ,  Hsiang-Hung Peng

    IPC: H01L23/544 ,  H01L27/092 ,  H01L27/02 ,  G03F9/00 ,  H01L21/8238

    Abstract: A semiconductor device includes a substrate including a plurality of chip areas and a scribe line defined thereon, and a mark pattern disposed in the scribe line. The mark pattern includes a plurality of unit cells immediately adjacent to each other, and each unit cell includes a first active region, a second active region isolated from the first active region, a plurality of first gate structures extending along a first direction and arranged along a second direction perpendicular to the first direction, and a plurality of first conductive structures. The first gate structures straddle the first active region and the second active region. The first conductive structures are disposed on the first active region, the second active region, and two opposite sides of the first gate structures.

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