公开(公告)号：US11984442B2

公开(公告)日：2024-05-14

申请号：US17715974

申请日：2022-04-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ruei-Yau Chen ,  Wei-Jen Wang ,  Kun-Yuan Wu ,  Chien-Fu Chen ,  Chen-Hsien Hsu

IPC: H01L27/02

CPC classification number: H01L27/0207

Abstract: A layout includes a first and a second standard cells abutting along a boundary line. The first cell includes first fins. An edge of the first fins closest to and away from the boundary line by a distance D1. A first gate line over-crossing the first fins protrudes from the edge by a length L1. The second cell includes second fins. An edge of the second fins closest to and away from the boundary line by a distance D2. A second gate line over-crossing the second fins protrudes from the edge by a length L2. Two first dummy gate lines at two sides of the first fins and two second dummy lines at two sides of the second fins are respectively away from the boundary line by a distance S. The lengths L1 and L2, the distances S, D1 and D2 have the relationships: L1≤D1−S, L2≤D2−S, and D1≠D2.

公开(公告)号：US20230097189A1

公开(公告)日：2023-03-30

申请号：US17868770

申请日：2022-07-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Hung Chen ,  Ruei-Yau Chen ,  Wei-Jen Wang ,  Kun-Yuan Wu ,  Chien-Fu Chen ,  Chen-Hsien Hsu

IPC: G06F30/392 ,  G06F30/30

Abstract: A method for forming an integrated circuit layout including at least two standard cells having different cell heights is disclosed. The standard cells respectively have a well boundary to divide a PMOS region and an NMOS region. The standard cells are abutted side by side along their side edges in a way that the well boundaries of the cells are aligned along the row direction. The power rail and the ground rail of one of the standard cells are shifted to align and connect to the power rail and the ground rail of the other one of the standard cells.

公开(公告)号：US11368146B2

公开(公告)日：2022-06-21

申请号：US16847682

申请日：2020-04-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Yuan Wu ,  Wei-Jen Wang ,  Chien-Fu Chen ,  Chen-Hsien Hsu ,  Yuan-Hui Chen ,  Cheng-Yang Tsai ,  Ruei-Yau Chen ,  Cheng-Tsung Ku ,  Zhi-Hong Huang ,  Yu-Lin Chen

IPC: H03K5/13 ,  H03K5/00

Abstract: A delay cell includes a cascode transistor and an inverter. The cascode transistor is used to receive a control voltage to generate a bias current, and includes a source terminal, a drain terminal, and a gate terminal receiving the control voltage. The inverter is coupled to the cascode transistor and used to generate an output signal according to the bias current in response to an input signal.

公开(公告)号：US20190088639A1

公开(公告)日：2019-03-21

申请号：US15987911

申请日：2018-05-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chen-Hsien Hsu ,  Chien-Fu Chen ,  Cheng-Yang Tsai ,  Wei-Jen Wang ,  Chao-Wei Lin ,  Zhi-Hong Huang ,  Cheng-Tsung Ku ,  Chin-Sheng Yang

IPC: H01L27/02 ,  H03K19/0948 ,  H01L23/528 ,  H01L27/092 ,  H01L23/522 ,  H03K19/20 ,  H01L29/167

Abstract: The present invention provides an integrated circuit with a standard cell of an inverter standard cell. The integrated circuit includes: a first metal line and a second metal line stretching along a first direction; a first dummy gate and a second dummy gate stretching along a second direction; Plural fin structures stretching along the first direction; A gate structure disposed on the fin structures and stretching along the second direction; Two long contact plugs disposed at one side of the gate structure; two short contact plugs disposed at the other side of the gate structure; a gate contact plug disposed on the gate structure; Plural via plugs disposed on the long contact plugs, the short contact plugs and the gate contact plugs; A metal layer includes the first metal line, the second metal line, a third metal line and a fourth metal line.

公开(公告)号：US20170039311A1

公开(公告)日：2017-02-09

申请号：US14852635

申请日：2015-09-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Wu ,  Chen-Hsien Hsu ,  Wei-Jen Wang ,  Chien-Fu Chen ,  Chien-Hung Chen

IPC: G06F17/50 ,  H01L27/02

CPC classification number: G06F17/5072 ,  H01L21/823437 ,  H01L27/0207 ,  H01L27/088

Abstract: A method for designing a semiconductor layout structure includes following steps. A first active feature group including at least a first active feature is received, and the first active feature includes a first channel length. A pair of first dummy features is introduced to form a first cell pattern. The first dummy features include a first dummy width. A first spacing width is defined between the first active feature group and one of the first dummy features and a third spacing width is defined between the first active feature group and the other first dummy feature. The first cell pattern includes a first cell width and a first poly pitch, and the first cell width is a multiple of the first pitch. The receiving of the first active feature group and the introducing of the first dummy features are performed in by at least a computer-aided design tool.

Abstract translation: 一种用于设计半导体布局结构的方法包括以下步骤。 接收包括至少第一活动特征的第一活动特征组，并且第一活动特征包括第一信道长度。 引入一对第一虚拟特征以形成第一细胞图案。 第一虚拟特征包括第一虚拟宽度。 在第一活动特征组和第一虚拟特征之一之间限定第一间隔宽度，并且在第一活动特征组和第二虚拟特征之间限定第三间隔宽度。 第一单元图案包括第一单元宽度和第一多段间距，并且第一单元宽度是第一间距的倍数。 至少由计算机辅助设计工具执行第一活动特征组的接收和第一虚拟特征的引入。