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    Phase-locked loop and method for controlling the same
    1.
    发明授权
    Phase-locked loop and method for controlling the same 有权
    锁相环及其控制方法

    公开(公告)号：US09160352B1

    公开(公告)日：2015-10-13

    申请号：US14287772

    申请日：2014-05-27

    Applicant: United Microelectronics Corp.

    Inventor： Po-Hua Chen ,  Yu-Yee Liow ,  Wen-Hong Hsu ,  Hsueh-Chen Cheng ,  Ya-Nan Mou ,  Yuan-Hui Chen

    IPC: H03L7/06 ,  H03L7/099 ,  H03L7/08 ,  H03L7/085

    CPC classification number: H03L3/00 ,  H03L7/089 ,  H03L7/099

    Abstract: A phase-locked loop (PLL) and a method for controlling the PLL are provided. The PLL includes a phase detector, a charge pump, a voltage-controlled oscillator (VCO), a feedback frequency divider, and a detector circuit. The phase detector generates a direction signal according to a comparison between phases of a first clock signal and a second clock signal. The charge pump converts the direction signal into a control voltage. The VCO generates a third clock signal. The control voltage controls a frequency of the third clock signal. The feedback frequency divider divides the frequency of the third clock signal to generate the second clock signal. The detector circuit sends a pulse signal to restart the VCO when the control voltage conforms to a preset condition.

    Abstract translation: 提供锁相环（PLL）和控制PLL的方法。 PLL包括相位检测器，电荷泵，压控振荡器（VCO），反馈分频器和检测器电路。 相位检测器根据第一时钟信号和第二时钟信号的相位之间的比较来产生方向信号。 电荷泵将方向信号转换成控制电压。 VCO产生第三个时钟信号。 控制电压控制第三时钟信号的频率。 反馈分频器分频第三时钟信号的频率以产生第二时钟信号。 当控制电压符合预设条件时，检测器电路发送脉冲信号重新启动VCO。

    VOLTAGE REGULATING CIRCUIT
    3.
    发明申请
    VOLTAGE REGULATING CIRCUIT 审中-公开

    公开(公告)号：US20180292848A1

    公开(公告)日：2018-10-11

    申请号：US15607266

    申请日：2017-05-26

    Applicant: United Microelectronics Corp.

    Inventor： Chai-Wei Fu ,  Cheng-Hsiao Lai ,  Ying-Ting Lin ,  Yuan-Hui Chen ,  Ya-Nan Mou ,  Yung-Hsiang Lin ,  Hsueh-Chen Cheng

    IPC: G05F1/44 ,  G05F1/46 ,  G05F1/575 ,  G05F1/56

    Abstract: A voltage regulating circuit provides a feedback voltage and an output voltage based on a power voltage. The voltage regulating circuit includes a reference voltage generator and a compensating circuit. The reference voltage generator receives the power voltage, produces the feedback voltage, and includes an impedance having first and second terminals. The second terminal is coupled to a ground voltage and a first current flows through the impedance at the first terminal to produce the feedback voltage. The compensating circuit includes a negative threshold voltage (NVT) transistor having a source terminal, a drain terminal and a gate terminal. The source terminal receives a power voltage, the drain terminal is connected to the gate terminal and coupled to the first terminal of the impedance through a path to add a second current to the first current when the NVT transistor is turned on under an operational condition at the FF corner.

    Voltage regulating circuit
    4.
    发明授权
    Voltage regulating circuit 有权

    公开(公告)号：US10095251B1

    公开(公告)日：2018-10-09

    申请号：US15607266

    申请日：2017-05-26

    Applicant: United Microelectronics Corp.

    Inventor： Chai-Wei Fu ,  Cheng-Hsiao Lai ,  Ying-Ting Lin ,  Yuan-Hui Chen ,  Ya-Nan Mou ,  Yung-Hsiang Lin ,  Hsueh-Chen Cheng

    IPC: G05F1/44 ,  G05F1/46 ,  G05F1/575 ,  G05F1/56

    Abstract: A voltage regulating circuit provides a feedback voltage and an output voltage based on a power voltage. The voltage regulating circuit includes a reference voltage generator and a compensating circuit. The reference voltage generator receives the power voltage, produces the feedback voltage, and includes an impedance having first and second terminals. The second terminal is coupled to a ground voltage and a first current flows through the impedance at the first terminal to produce the feedback voltage. The compensating circuit includes a negative threshold voltage (NVT) transistor having a source terminal, a drain terminal and a gate terminal. The source terminal receives a power voltage, the drain terminal is connected to the gate terminal and coupled to the first terminal of the impedance through a path to add a second current to the first current when the NVT transistor is turned on under an operational condition at the FF corner.

    Static random access memory
    7.
    发明授权
    Static random access memory 有权

    公开(公告)号：US10777260B1

    公开(公告)日：2020-09-15

    申请号：US16655220

    申请日：2019-10-16

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Zih-Yu Chiu ,  Hsin-Wen Chen ,  Ya-Nan Mou ,  Yuan-Hui Chen ,  Chung-Cheng Tsai

    IPC: G11C11/00 ,  G11C11/412 ,  G11C11/419 ,  H01L27/11

    Abstract: An SRAM cell includes two inverters and three transistors. The first inverter includes a first end coupled to a first storage node and a second end coupled to a second storage node. The second inverter includes a first end coupled to the second storage node and a second end coupled to the first storage node. The first transistor includes a first end coupled to the first storage node, a second end and a control end. The second transistor includes a first end coupled to the second end of the first transistor, a second end coupled to a first bit line, and a control end. The third transistor includes a first end coupled between the second end of the first transistor and the first end of the second transistor, a second end, and a control end coupled to the first storage node.

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