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    STATIC RANDOM ACCESS MEMORY UNIT STRUCTURE AND STATIC RANDOM ACCESS MEMORY LAYOUT STRUCTURE
    2.
    发明申请
    STATIC RANDOM ACCESS MEMORY UNIT STRUCTURE AND STATIC RANDOM ACCESS MEMORY LAYOUT STRUCTURE 有权
    静态随机访问存储单元结构和静态随机访问存储器布局结构

    公开(公告)号：US20170018302A1

    公开(公告)日：2017-01-19

    申请号：US14822911

    申请日：2015-08-11

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Tan-Ya Yin ,  Ming-Jui Chen ,  Chia-Wei Huang ,  Yu-Cheng Tung ,  Chin-Sheng Yang

    IPC: G11C11/412 ,  H01L27/02 ,  H01L27/11

    CPC classification number: G11C11/417 ,  G11C11/412 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/1104

    Abstract: A static random access memory unit structure and layout structure includes two pull-up transistors, two pull-down transistors, two slot contact plugs, and two metal-zero interconnects. Each metal-zero interconnect is disposed on each slot contact plug and a gate of each pull-up transistor, in which, each slot contact plug crosses a drain of each pull-down transistor and a drain of each pull-up transistor and extends to cross an end of each metal-zero interconnect. A gap between the slot contact plugs is smaller than a gap between the metal-zero interconnects.

    Abstract translation: 静态随机存取存储器单元结构和布局结构包括两个上拉晶体管，两个下拉晶体管，两个槽接触插头和两个金属零互连。 每个金属零互连设置在每个槽接触插头和每个上拉晶体管的栅极上，每个槽接触插塞跨越每个下拉晶体管的漏极和每个上拉晶体管的漏极延伸到 跨越每个金属零互连的一端。 槽接触插塞之间的间隙小于金属零互连之间的间隙。

    Sonos device
    3.
    发明授权
    Sonos device 有权
    Sonos设备

    公开(公告)号：US09508734B2

    公开(公告)日：2016-11-29

    申请号：US15077892

    申请日：2016-03-22

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chin-Sheng Yang ,  Chien-Hung Chen

    IPC: H01L29/792 ,  H01L27/115 ,  H01L29/66 ,  H01L29/423 ,  H01L21/28

    CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

    Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) device is disclosed. The SONOS device includes a substrate; a first oxide layer on the substrate; a silicon-rich trapping layer on the first oxide layer; a nitrogen-containing layer on the silicon-rich trapping layer; a silicon-rich oxide layer on the nitrogen-containing layer; and a polysilicon layer on the silicon-rich oxide layer.

    Abstract translation: 公开了一种氧化硅 - 氮化物 - 氧化物 - 硅（SONOS）器件。 SONOS器件包括衬底; 衬底上的第一氧化物层; 在所述第一氧化物层上的富硅捕获层; 富硅捕获层上的含氮层; 含氮层上的富氧氧化物层; 和富硅氧化物层上的多晶硅层。

    Semiconductor device and operating method thereof
    4.
    发明授权
    Semiconductor device and operating method thereof 有权
    半导体器件及其操作方法

    公开(公告)号：US09490360B2

    公开(公告)日：2016-11-08

    申请号：US14183541

    申请日：2014-02-19

    Applicant: United Microelectronics Corp.

    Inventor： Ming-Shing Chen ,  Ming-Hui Chang ,  Wei-Ting Wu ,  Ying-Chou Lai ,  Horng-Nan Chern ,  Chorng-Lih Young ,  Chin-Sheng Yang

    IPC: H01L21/761 ,  H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/49 ,  H01L29/66

    CPC classification number: H01L29/7816 ,  H01L21/761 ,  H01L29/0649 ,  H01L29/402 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/7835

    Abstract: Provided is a semiconductor device including a P-type substrate, a P-type first well region, an N-type second well region, a gate, N-type source and drain regions, a dummy gate and an N-type deep well region. The first well region is in the substrate. The second well region is in the substrate proximate to the first well region. The gate is on the substrate and covers a portion of the first well region and a portion of the second well region. The source region is in the first well region at one side of the gate. The drain region is in the second well region at another side of the gate. The dummy gate is on the substrate between the gate and the drain region. The deep well region is in the substrate and surrounds the first and second well regions. An operation method of the semiconductor device is further provided.

    Abstract translation: 提供一种半导体器件，包括P型衬底，P型第一阱区，N型第二阱区，栅极，N型源极和漏极区，虚拟栅极和N型阱阱区域 。 第一阱区位于衬底中。 第二阱区位于靠近第一阱区的衬底中。 栅极位于基板上并且覆盖第一阱区域的一部分和第二阱区域的一部分。 源极区位于栅极一侧的第一阱区中。 漏极区域位于栅极另一侧的第二阱区域中。 虚拟栅极位于栅极和漏极区域之间的衬底上。 深井区域位于基板中并围绕第一和第二井区域。 还提供了一种半导体器件的操作方法。

    SONOS DEVICE
    7.
    发明申请
    SONOS DEVICE 有权
    SONOS设备

    公开(公告)号：US20160204121A1

    公开(公告)日：2016-07-14

    申请号：US15077892

    申请日：2016-03-22

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chin-Sheng Yang ,  Chien-Hung Chen

    IPC: H01L27/115 ,  H01L29/423 ,  H01L29/792

    CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

    Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) device is disclosed. The SONOS device includes a substrate; a first oxide layer on the substrate; a silicon-rich trapping layer on the first oxide layer; a nitrogen-containing layer on the silicon-rich trapping layer; a silicon-rich oxide layer on the nitrogen-containing layer; and a polysilicon layer on the silicon-rich oxide layer.

    Abstract translation: 公开了一种氧化硅 - 氮化物 - 氧化物 - 硅（SONOS）器件。 SONOS器件包括衬底; 衬底上的第一氧化物层; 在所述第一氧化物层上的富硅捕获层; 富硅捕获层上的含氮层; 含氮层上的富硅氧化物层; 和富硅氧化物层上的多晶硅层。

    INTEGRATED CIRCUITS WITH STANDARD CELL
    9.
    发明申请
    INTEGRATED CIRCUITS WITH STANDARD CELL 审中-公开

    公开(公告)号：US20190088638A1

    公开(公告)日：2019-03-21

    申请号：US15785447

    申请日：2017-10-17

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chen-Hsien Hsu ,  Chien-Fu Chen ,  Cheng-Yang Tsai ,  Wei-Jen Wang ,  Chao-Wei Lin ,  Zhi-Hong Huang ,  Cheng-Tsung Ku ,  Chin-Sheng Yang

    IPC: H01L27/02 ,  H03K19/0948 ,  H01L23/528 ,  H01L27/092 ,  H01L23/522

    Abstract: The present invention provides an integrated circuit with a standard cell of an inverter. The integrated circuit includes: a first metal line and a second metal line stretching along a first direction; a first dummy gate and a second dummy gate stretching along a second direction; Plural fin structures stretching along the first direction; A gate structure disposed on the fin structures and stretching along the second direction; Two long contact plugs disposed at one side of the gate structure; two short contact plugs disposed at the other side of the gate structure; a gate contact plug disposed on the gate structure; Plural via plugs disposed on the long contact plugs, the short contact plugs and the gate contact plugs; A metal layer includes the first metal line, the second metal line, a third metal line and a fourth metal line.

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