中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

9 records (took 0.013 seconds)

    INTEGRATED CIRCUITS WITH STANDARD CELL
    4.
    发明申请
    INTEGRATED CIRCUITS WITH STANDARD CELL 审中-公开

    公开(公告)号：US20190088638A1

    公开(公告)日：2019-03-21

    申请号：US15785447

    申请日：2017-10-17

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chen-Hsien Hsu ,  Chien-Fu Chen ,  Cheng-Yang Tsai ,  Wei-Jen Wang ,  Chao-Wei Lin ,  Zhi-Hong Huang ,  Cheng-Tsung Ku ,  Chin-Sheng Yang

    IPC: H01L27/02 ,  H03K19/0948 ,  H01L23/528 ,  H01L27/092 ,  H01L23/522

    Abstract: The present invention provides an integrated circuit with a standard cell of an inverter. The integrated circuit includes: a first metal line and a second metal line stretching along a first direction; a first dummy gate and a second dummy gate stretching along a second direction; Plural fin structures stretching along the first direction; A gate structure disposed on the fin structures and stretching along the second direction; Two long contact plugs disposed at one side of the gate structure; two short contact plugs disposed at the other side of the gate structure; a gate contact plug disposed on the gate structure; Plural via plugs disposed on the long contact plugs, the short contact plugs and the gate contact plugs; A metal layer includes the first metal line, the second metal line, a third metal line and a fourth metal line.

    Speed-up charge pump and phase-locked loop and method for operating the same
    8.
    发明授权
    Speed-up charge pump and phase-locked loop and method for operating the same 有权

    公开(公告)号：US11115033B1

    公开(公告)日：2021-09-07

    申请号：US17065414

    申请日：2020-10-07

    Applicant: United Microelectronics Corp.

    Inventor： Kun-Yuan Wu ,  Wei-Jen Wang ,  Chien-Fu Chen ,  Cheng-Yang Tsai ,  Ruei-Yau Chen ,  Yu-Lin Chen

    IPC: H03L7/089 ,  H03L7/099

    Abstract: A speed-up charge pump includes a first charge pump for receiving an up signal and a down signal in digital form to produce a first voltage control signal at an output node. Further, at least one speed-up phase detector includes a first circuit path to receive the up signal and delay the up signal by a predetermined delay as a delay up signal and operate the up signal and the delay up signal by AND logic into an auxiliary up signal; and a second circuit path to receive the down signal and delay the down signal by the predetermined delay as a delay down signal and operate the down signal and the delay down signal by AND logic into an auxiliary down signal. A second charge pump is respectively receiving the auxiliary up and down signals to produce a second voltage control signal also at the output node.

    Integrated circuits with standard cell
    9.
    发明授权
    Integrated circuits with standard cell 有权

    公开(公告)号：US10090289B1

    公开(公告)日：2018-10-02

    申请号：US15813163

    申请日：2017-11-15

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chen-Hsien Hsu ,  Chien-Fu Chen ,  Cheng-Yang Tsai ,  Wei-Jen Wang ,  Chao-Wei Lin ,  Zhi-Hong Huang ,  Cheng-Tsung Ku ,  Chin-Sheng Yang

    IPC: H01L27/02 ,  H01L23/522 ,  H01L27/088 ,  H01L23/528

    Abstract: The present invention provides an integrated circuit with a dummy standard cell. The integrated circuit includes: a first metal line and a second metal line stretching along a first direction; a first dummy gate and a second dummy gate stretching along a second direction; Plural fin structures stretching along the first direction; A gate structure disposed on the fin structures and stretching along the second direction; Plural sets of short contact plug and long contact plug disposed between the first dummy gate, the second dummy gate and the gate structures; a doping region overlaps with the long contact plugs; a gate contact plug disposed on the gate structures; plural contact plugs disposed on and electrical contact the long contact plugs; A metal layer includes the first metal line, the second metal line.

Patent Agency Ranking