公开(公告)号：US10262982B2

公开(公告)日：2019-04-16

申请号：US15785447

申请日：2017-10-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chen-Hsien Hsu ,  Chien-Fu Chen ,  Cheng-Yang Tsai ,  Wei-Jen Wang ,  Chao-Wei Lin ,  Zhi-Hong Huang ,  Cheng-Tsung Ku ,  Chin-Sheng Yang

IPC: H01L27/02 ,  H03K19/0948 ,  H01L23/528 ,  H01L23/522 ,  H01L27/092 ,  H01L29/167 ,  H03K19/20

Abstract: The present invention provides an integrated circuit with a standard cell of an inverter. The integrated circuit includes: a first metal line and a second metal line stretching along a first direction; a first dummy gate and a second dummy gate stretching along a second direction; Plural fin structures stretching along the first direction; A gate structure disposed on the fin structures and stretching along the second direction; Two long contact plugs disposed at one side of the gate structure; two short contact plugs disposed at the other side of the gate structure; a gate contact plug disposed on the gate structure; Plural via plugs disposed on the long contact plugs, the short contact plugs and the gate contact plugs; A metal layer includes the first metal line, the second metal line, a third metal line and a fourth metal line.

公开(公告)号：US20210288634A1

公开(公告)日：2021-09-16

申请号：US16847682

申请日：2020-04-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Yuan Wu ,  Wei-Jen Wang ,  Chien-Fu Chen ,  Chen-Hsien Hsu ,  Yuan-Hui Chen ,  Cheng-Yang Tsai ,  Ruei-Yau Chen ,  Cheng-Tsung Ku ,  Zhi-Hong Huang ,  Yu-Lin Chen

IPC: H03K5/13

Abstract: A delay cell includes a cascode transistor and an inverter. The cascode transistor is used to receive a control voltage to generate a bias current, and includes a source terminal, a drain terminal, and a gate terminal receiving the control voltage. The inverter is coupled to the cascode transistor and used to generate an output signal according to the bias current in response to an input signal.

公开(公告)号：US11348847B2

公开(公告)日：2022-05-31

申请号：US16249812

申请日：2019-01-16

Applicant: United Microelectronics Corp.

Inventor： Kun-Yuan Wu ,  Wei-Jen Wang ,  Chien-Fu Chen ,  Chen-Hsien Hsu ,  Yuan-Hui Chen ,  Ruei-Yau Chen ,  Cheng-Tsung Ku ,  Zhi-Hong Huang ,  Cheng-Yang Tsai ,  Yu-Lin Chen

IPC: H01L21/66 ,  G01R31/28 ,  H03K3/03 ,  H01L23/544

Abstract: The invention provides a testkey detection circuit, including a plurality of oscillators and a driving circuit. Each of the oscillators has an enable terminal, a voltage terminal and an output terminal, wherein the enable terminals are connected to a common enable terminal. The driving circuit receives the output terminals of the oscillators and increases a driving level of a selected one of the output terminals as a frequency output.

公开(公告)号：US10090289B1

公开(公告)日：2018-10-02

申请号：US15813163

申请日：2017-11-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chen-Hsien Hsu ,  Chien-Fu Chen ,  Cheng-Yang Tsai ,  Wei-Jen Wang ,  Chao-Wei Lin ,  Zhi-Hong Huang ,  Cheng-Tsung Ku ,  Chin-Sheng Yang

IPC: H01L27/02 ,  H01L23/522 ,  H01L27/088 ,  H01L23/528

Abstract: The present invention provides an integrated circuit with a dummy standard cell. The integrated circuit includes: a first metal line and a second metal line stretching along a first direction; a first dummy gate and a second dummy gate stretching along a second direction; Plural fin structures stretching along the first direction; A gate structure disposed on the fin structures and stretching along the second direction; Plural sets of short contact plug and long contact plug disposed between the first dummy gate, the second dummy gate and the gate structures; a doping region overlaps with the long contact plugs; a gate contact plug disposed on the gate structures; plural contact plugs disposed on and electrical contact the long contact plugs; A metal layer includes the first metal line, the second metal line.

公开(公告)号：US10319709B2

公开(公告)日：2019-06-11

申请号：US15987911

申请日：2018-05-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chen-Hsien Hsu ,  Chien-Fu Chen ,  Cheng-Yang Tsai ,  Wei-Jen Wang ,  Chao-Wei Lin ,  Zhi-Hong Huang ,  Cheng-Tsung Ku ,  Chin-Sheng Yang

IPC: H01L27/02 ,  H01L27/092 ,  H01L23/522 ,  H01L23/528 ,  H03K19/0948 ,  H03K19/20 ,  H01L29/167

Abstract: The present invention provides an integrated circuit with a standard cell of an inverter standard cell. The integrated circuit includes: a first metal line and a second metal line stretching along a first direction; a first dummy gate and a second dummy gate stretching along a second direction; Plural fin structures stretching along the first direction; A gate structure disposed on the fin structures and stretching along the second direction; Two long contact plugs disposed at one side of the gate structure; two short contact plugs disposed at the other side of the gate structure; a gate contact plug disposed on the gate structure; Plural via plugs disposed on the long contact plugs, the short contact plugs and the gate contact plugs; A metal layer includes the first metal line, the second metal line, a third metal line and a fourth metal line.

公开(公告)号：US20190088638A1

公开(公告)日：2019-03-21

申请号：US15785447

申请日：2017-10-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chen-Hsien Hsu ,  Chien-Fu Chen ,  Cheng-Yang Tsai ,  Wei-Jen Wang ,  Chao-Wei Lin ,  Zhi-Hong Huang ,  Cheng-Tsung Ku ,  Chin-Sheng Yang

IPC: H01L27/02 ,  H03K19/0948 ,  H01L23/528 ,  H01L27/092 ,  H01L23/522

Abstract: The present invention provides an integrated circuit with a standard cell of an inverter. The integrated circuit includes: a first metal line and a second metal line stretching along a first direction; a first dummy gate and a second dummy gate stretching along a second direction; Plural fin structures stretching along the first direction; A gate structure disposed on the fin structures and stretching along the second direction; Two long contact plugs disposed at one side of the gate structure; two short contact plugs disposed at the other side of the gate structure; a gate contact plug disposed on the gate structure; Plural via plugs disposed on the long contact plugs, the short contact plugs and the gate contact plugs; A metal layer includes the first metal line, the second metal line, a third metal line and a fourth metal line.

公开(公告)号：US11368146B2

公开(公告)日：2022-06-21

申请号：US16847682

申请日：2020-04-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Yuan Wu ,  Wei-Jen Wang ,  Chien-Fu Chen ,  Chen-Hsien Hsu ,  Yuan-Hui Chen ,  Cheng-Yang Tsai ,  Ruei-Yau Chen ,  Cheng-Tsung Ku ,  Zhi-Hong Huang ,  Yu-Lin Chen

IPC: H03K5/13 ,  H03K5/00

Abstract: A delay cell includes a cascode transistor and an inverter. The cascode transistor is used to receive a control voltage to generate a bias current, and includes a source terminal, a drain terminal, and a gate terminal receiving the control voltage. The inverter is coupled to the cascode transistor and used to generate an output signal according to the bias current in response to an input signal.

公开(公告)号：US20190088639A1

公开(公告)日：2019-03-21

申请号：US15987911

申请日：2018-05-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chen-Hsien Hsu ,  Chien-Fu Chen ,  Cheng-Yang Tsai ,  Wei-Jen Wang ,  Chao-Wei Lin ,  Zhi-Hong Huang ,  Cheng-Tsung Ku ,  Chin-Sheng Yang

IPC: H01L27/02 ,  H03K19/0948 ,  H01L23/528 ,  H01L27/092 ,  H01L23/522 ,  H03K19/20 ,  H01L29/167

Abstract: The present invention provides an integrated circuit with a standard cell of an inverter standard cell. The integrated circuit includes: a first metal line and a second metal line stretching along a first direction; a first dummy gate and a second dummy gate stretching along a second direction; Plural fin structures stretching along the first direction; A gate structure disposed on the fin structures and stretching along the second direction; Two long contact plugs disposed at one side of the gate structure; two short contact plugs disposed at the other side of the gate structure; a gate contact plug disposed on the gate structure; Plural via plugs disposed on the long contact plugs, the short contact plugs and the gate contact plugs; A metal layer includes the first metal line, the second metal line, a third metal line and a fourth metal line.