公开(公告)号：US20240345469A1

公开(公告)日：2024-10-17

申请号：US18308670

申请日：2023-04-27

Applicant: United Microelectronics Corp.

Inventor： Chia-Chen Sun ,  En-Chiuan Liou ,  Song-Yi Lin

IPC: G03F1/38

CPC classification number: G03F1/38 ,  H01L21/0273

Abstract: A photomask structure including a layout pattern, a first L-type assist pattern, and a second L-type assist pattern is provided. An end portion of the layout pattern includes a first edge, a second edge, and a third edge. The second edge is connected to one end of the first edge, and the third edge is connected to another end of the first edge. The first L-type assist pattern is located between the second L-type assist pattern and the first edge. The layout pattern, the first L-type assist pattern, and the second L-type assist pattern are separated from each other. The first L-type assist pattern surrounds the first edge and the second edge. The second L-type assist pattern surrounds the first edge and the third edge.

公开(公告)号：US10566290B2

公开(公告)日：2020-02-18

申请号：US15715184

申请日：2017-09-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Chen Sun ,  Yu-Cheng Tung ,  Sheng-Yuan Hsueh ,  Fan-Wei Lin

IPC: H01L23/544 ,  H01L21/66 ,  G01B21/24 ,  G03F7/20 ,  G01B21/20 ,  G03F9/00

Abstract: The present invention provides an alignment mark, the alignment mark includes at least one dummy mark pattern in a first layer comprises a plurality of dummy mark units arranged along a first direction, and at least one first mark pattern located in a second layer disposed above the first layer, the first mark pattern comprises a plurality of first mark units, each of the first mark units being arranged in a first direction. When viewed in a top view, the first mark pattern completely covers the dummy mark pattern, and the size of each dummy mark unit is smaller than each first mark unit. In addition, each dummy mark unit of the dummy mark pattern has a first width, each first mark unit of the first mark pattern has a second width, and the first width is smaller than half of the second width.

公开(公告)号：US20190317393A1

公开(公告)日：2019-10-17

申请号：US15978215

申请日：2018-05-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Chen Sun ,  Yu-Cheng Tung ,  Sheng-Yuan Hsueh

IPC: G03F1/36 ,  G06F17/50

Abstract: A mask includes a substrate, a main pattern, a first assist pattern, and a second assist pattern. The main pattern is disposed on the substrate. The main pattern includes a first pattern and second patterns. Two of the second patterns are disposed at two opposite sides of the first pattern in a first direction. The first assist pattern is disposed on the substrate and disposed in the main pattern. The second assist pattern is disposed on the substrate and disposed outside the main pattern. The first assist pattern disposed in the main pattern may be used to improve the pattern transferring performance in a photolithography process using the mask.

公开(公告)号：US10082471B2

公开(公告)日：2018-09-25

申请号：US15396805

申请日：2017-01-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yung-Teng Tsai ,  Hung-Chin Lin ,  Chia-Chen Sun ,  Chih-Yu Wu ,  Jun-Ming Chen ,  Chung-Chih Hung ,  Sheng-Chieh Chen

IPC: B81B3/00 ,  G01N21/93 ,  H01L21/66 ,  H01L23/544 ,  G01N21/95

CPC classification number: H01L23/544 ,  H01L22/12 ,  H01L2223/54426 ,  H01L2223/5446

Abstract: A semiconductor structure includes a wafer comprising a plurality of viewing fields defined thereon, a plurality of dies defined by a scribe line formed in each viewing field, a plurality of mark patterns formed in the scribe line, and a plurality of anchor pattern respectively formed in the review fields, the anchor patterns being different from the mark patterns.

公开(公告)号：US20180247005A1

公开(公告)日：2018-08-30

申请号：US15462900

申请日：2017-03-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Chen Sun ,  Yu-Cheng Tung

IPC: G06F17/50

CPC classification number: G06F17/5072

Abstract: A method for a semiconductor layout pattern decomposition includes following steps. (a) receiving a semiconductor layout pattern; (b) performing a first separation/decomposition to the semiconductor layout pattern to obtain a grille pattern and a non-grille pattern; (c) recognizing a plurality of intersection regions in the grille pattern and alternately marking the intersection regions with a first region and a second region; (d) performing a second separation/decomposition to the grille pattern to obtain a plurality of first sub-patterns and a plurality of second sub-patterns perpendicular to each other, the first sub-patterns including the first regions, the second sub-patterns including the second regions; and (e) introducing a plurality of first assistance features on the first regions in the first sub-patterns and on the second regions on the second regions in the second sub-patterns, respectively. The step (a) to the step (e) are implemented using a computer.