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    RRAM STRUCTURE AND METHOD OF FABRICATING THE SAME
    21.
    发明申请
    RRAM STRUCTURE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20210217813A1

    公开(公告)日：2021-07-15

    申请号：US16794194

    申请日：2020-02-18

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wen-Jen Wang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

    IPC: H01L27/24 ,  H01L45/00

    Abstract: An RRAM structure includes a substrate. The substrate is divided into a memory cell region and a logic device region. A metal plug is disposed within the memory cell region. An RRAM is disposed on and contacts the metal plug. The RRAM includes a top electrode, a variable resistive layer, and a bottom electrode. The variable resistive layer is disposed between the top electrode and the bottom electrode. The variable resistive layer includes a first bottom surface. The bottom electrode includes a first top surface. The first bottom surface and the first top surface are coplanar. The first bottom surface only overlaps and contacts part of the first top surface.

    SEMICONDUCTOR MEMORY DEVICE AND FABRICATION METHOD THEREOF
    22.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND FABRICATION METHOD THEREOF 审中-公开

    公开(公告)号：US20200185399A1

    公开(公告)日：2020-06-11

    申请号：US16792847

    申请日：2020-02-17

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wen-Jen Wang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

    IPC: H01L27/11568 ,  H01L21/28 ,  H01L29/792

    Abstract: A method for fabricating a semiconductor memory device is disclosed. A substrate having a main surface is provided. A memory gate is formed on the main surface of the substrate. The memory has a first sidewall and a second sidewall opposite to the first sidewall. A control gate is formed in proximity to the memory gate. The control gate has a third sidewall directly facing the second sidewall, and a fourth sidewall opposite to the third sidewall. A gap is formed between the second sidewall of the memory gate and the third sidewall of the control gate. A first single spacer structure is formed on the first sidewall of the memory gate and a second single spacer structure on the fourth sidewall of the control gate. A gap-filling layer is formed to fill up the gap.

    RESISTIVE MEMORY STRUCTURE AND MANUFACTURING METHOD THEREOF
    24.
    发明公开
    RESISTIVE MEMORY STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20230354724A1

    公开(公告)日：2023-11-02

    申请号：US17750425

    申请日：2022-05-23

    Applicant: United Microelectronics Corp.

    Inventor： Wen-Jen Wang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

    IPC: H01L45/00 ,  H01L49/02

    CPC classification number: H01L45/1253 ,  H01L45/146 ,  H01L28/24 ,  H01L45/1625 ,  H01L45/1616

    Abstract: Provided is a resistive memory structure and a manufacturing method thereof. The resistive memory structure includes a substrate, a dielectric layer, a resistive memory device, a hard mask layer, and a spacer. The dielectric layer is located on the substrate. The dielectric layer has an opening. The resistive memory device is located in the opening and has a protrusion outside the opening. The resistive memory device includes a first electrode, a variable resistance layer, and a second electrode. The variable resistance layer is located on the first electrode. The second electrode is located on the variable resistance layer. The hard mask layer covers a top surface of the variable resistance layer. The spacer covers a sidewall of the variable resistance layer in the protrusion.

    Semiconductor device and method for forming the same
    25.
    发明授权
    Semiconductor device and method for forming the same 有权

    公开(公告)号：US11765915B2

    公开(公告)日：2023-09-19

    申请号：US17870814

    申请日：2022-07-21

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wen-Jen Wang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

    IPC: H10B63/00 ,  H10N70/00

    CPC classification number: H10B63/80 ,  H10N70/063 ,  H10N70/826

    Abstract: A semiconductor device includes a substrate having a memory region and a logic region. A first dielectric layer is disposed on the substrate. A first conductive structure and a second conductive structure are respectively formed in the first dielectric layer on the memory region and the logic region. A memory cell is formed on the first dielectric layer and directly contacts a top surface of the first conductive structure. A first cap layer continuously covers a top surface and a sidewall of the memory cell and directly contacts a top surface of the second conductive structure. A second dielectric layer is formed on the first cap layer. A third conductive structure penetrates through the second dielectric layer and the first cap layer to contact the memory cell.

    RESISTIVE RANDOM-ACCESS MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
    26.
    发明申请
    RESISTIVE RANDOM-ACCESS MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20230020564A1

    公开(公告)日：2023-01-19

    申请号：US17404934

    申请日：2021-08-17

    Applicant: United Microelectronics Corp.

    Inventor： Wen-Jen Wang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

    IPC: H01L45/00 ,  H01L27/24

    Abstract: Provided is a resistive random-access memory device, including a dielectric layer located on a substrate, a first electrode which is a column located on the dielectric layer, a second electrode covering a top surface and a sidewall of the first electrode, and a variable resistance layer sandwiched between the top surface of the first electrode and the second electrode and between the sidewall of the first electrode and the second electrode and located between the second electrode and the dielectric layer.

    Method for manufacturing a resistive random access memory structure
    28.
    发明授权
    Method for manufacturing a resistive random access memory structure 有权

    公开(公告)号：US11538990B2

    公开(公告)日：2022-12-27

    申请号：US17371376

    申请日：2021-07-09

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wen-Jen Wang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

    IPC: H01L45/00 ,  H01L27/24

    Abstract: A method for forming a resistive random access memory structure. The resistive random access memory structure includes a bottom electrode; a variable resistance layer disposed on the bottom electrode; a top electrode disposed on the variable resistance layer; a protection layer surrounding the variable resistance layer, wherein a top surface of the protection layer and a top surface of the top electrode are coplanar; and an upper interconnect structure disposed on the top electrode, wherein the upper interconnect structure is electrically connected to the top electrode and directly contacts a sidewall of the protection layer.

    SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME
    29.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME 有权

    公开(公告)号：US20220102429A1

    公开(公告)日：2022-03-31

    申请号：US17084609

    申请日：2020-10-29

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wen-Jen Wang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

    IPC: H01L27/24 ,  H01L45/00

    Abstract: A semiconductor device includes a substrate having a memory region and a logic region. A first dielectric layer is disposed on the substrate. A first conductive structure and a second conductive structure are formed in the first dielectric layer and respectively on the memory region and the logic region of the substrate. A memory cell is disposed on the first dielectric layer and directly contacts a top surface of the first conductive structure. A first cap layer is formed on the first dielectric layer and continuously covers a top surface and a sidewall of the memory cell and a top surface of the second conductive structure. A second dielectric layer is formed on the first cap. A third conductive structure is formed in the second dielectric layer and penetrates through the first cap layer to contacts the memory cell.

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