公开(公告)号：US10312250B1

公开(公告)日：2019-06-04

申请号：US15878278

申请日：2018-01-23

Applicant: United Microelectronics Corp.

Inventor： Hsuan-Chun Tseng ,  Hsueh-Chun Hsiao ,  Tzu-Yun Chang ,  Chi-Cheng Huang ,  Ping-Chia Shih

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/266 ,  H01L21/311 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11534 ,  H01L27/11573 ,  H01L27/11578

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a plurality of isolation structures, a charge storage layer, and a conductive layer. The substrate has a memory region and a logic region. The substrate in the memory region has a plurality of semiconductor fins. The isolation structures are disposed in the substrate to isolate the semiconductor fins. The semiconductor fins are protruded beyond the isolation structures. The charge storage layer covers the semiconductor fins. The conductive layer is disposed across the semiconductor fins and the isolation structures such that the charge storage layer is disposed between the conductive layer and the semiconductor fins.

公开(公告)号：US09691671B2

公开(公告)日：2017-06-27

申请号：US14472348

申请日：2014-08-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tse-Min Chao ,  Tzu-Yun Chang ,  Hsueh-Chun Hsiao

IPC: H01L21/66

CPC classification number: H01L22/34

Abstract: The present invention provides a test key array including a lower conductive pattern, and the lower conductive pattern includes a plurality of first L-shaped traces parallel to each other, an upper conductive pattern, where the upper conductive pattern includes a plurality of second L-shaped traces parallel to each other, the lower conductive pattern crosses to the upper conductive pattern, and a plurality of cross regions are defined between the lower conductive pattern and the upper conductive pattern, and a plurality of conductive plugs, disposed on parts of the cross regions, electrically connecting to the lower conductive pattern and the upper conductive pattern.

公开(公告)号：US20160064295A1

公开(公告)日：2016-03-03

申请号：US14472348

申请日：2014-08-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tse-Min Chao ,  Tzu-Yun Chang ,  Hsueh-Chun Hsiao

IPC: H01L21/66

CPC classification number: H01L22/34

Abstract: The present invention provides a test key array including a lower conductive pattern, and the lower conductive pattern includes a plurality of first L-shaped traces parallel to each other, an upper conductive pattern, where the upper conductive pattern includes a plurality of second L-shaped traces parallel to each other, the lower conductive pattern crosses to the upper conductive pattern, and a plurality of cross regions are defined between the lower conductive pattern and the upper conductive pattern, and a plurality of conductive plugs, disposed on parts of the cross regions, electrically connecting to the lower conductive pattern and the upper conductive pattern.

Abstract translation: 本发明提供了包括下导电图案的测试键阵列，并且下导电图案包括彼此平行的多个第一L形迹线，上导电图案，其中上导电图案包括多个第二L形迹线， 形状的迹线彼此平行，下导电图案与上导电图案交叉，并且在下导电图案和上导电图案之间限定多个交叉区域，以及多个导电插头，设置在十字的部分上 区域，电连接到下导电图案和上导电图案。