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    Method for manufacturing silicon—oxide—nitride—oxide—silicon (SONOS) non-volatile memory cell
    4.
    发明授权
    Method for manufacturing silicon—oxide—nitride—oxide—silicon (SONOS) non-volatile memory cell 有权
    制造氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）非易失性存储单元的方法

    公开(公告)号：US09202701B1

    公开(公告)日：2015-12-01

    申请号：US14572805

    申请日：2014-12-17

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Kun-I Chou ,  Chi-Cheng Huang ,  Yu-Chun Chang ,  Ling-Hsiu Chou ,  Tseng-Fang Dai ,  Jheng-Jie Huang ,  Ping-Chia Shih

    IPC: H01L21/336 ,  H01L21/28 ,  H01L27/115

    CPC classification number: H01L21/28282 ,  H01L29/66833 ,  H01L29/792

    Abstract: A method for manufacturing a silicon-oxide-nitride-oxide-silicon non-volatile memory cell includes following steps. An implant region is formed in a substrate. A first oxide layer, a nitride layer, and a second oxide layer are formed and stacked on the substrate. A density of the second oxide layer is higher than a density of the first oxide layer. A first photoresist pattern is formed on the second oxide layer and corresponding to the implant region. A first wet etching process is then performed to form an oxide hard mask. A second wet etching process is performed to remove the nitride layer exposed by the oxide hard mask to form a nitride pattern. A cleaning process is then performed to remove the oxide hard mask and the first oxide layer exposed by the nitride pattern, and a gate oxide layer is then formed on the nitride pattern.

    Abstract translation: 一种用于制造氧化硅 - 氮化物 - 氧化物 - 硅非易失性存储单元的方法包括以下步骤。 在衬底中形成植入区域。 形成第一氧化物层，氮化物层和第二氧化物层并堆叠在基板上。 第二氧化物层的密度高于第一氧化物层的密度。 第一光致抗蚀剂图案形成在第二氧化物层上并对应于植入区域。 然后进行第一湿法蚀刻工艺以形成氧​​化物硬掩模。 执行第二湿法蚀刻工艺以去除由氧化物硬掩模暴露的氮化物层以形成氮化物图案。 然后进行清洁处理以除去由氮化物图案暴露的氧化物硬掩模和第一氧化物层，然后在氮化物图案上形成栅极氧化物层。

    Semiconductor device and fabrication method thereof
    5.
    发明申请
    Semiconductor device and fabrication method thereof 有权
    半导体器件及其制造方法

    公开(公告)号：US20140353739A1

    公开(公告)日：2014-12-04

    申请号：US13909057

    申请日：2013-06-03

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hsiang-Chen Lee ,  Ping-Chia Shih ,  Chi-Cheng Huang ,  Wan-Fang Chung ,  Yu-Chun Chang ,  Je-Yi Su

    IPC: H01L29/66 ,  H01L29/792

    CPC classification number: H01L29/66833 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/0332 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/42348 ,  H01L29/792 ,  H01L29/7923

    Abstract: A semiconductor device including a first gate structure and a second gate structure immediately adjacent to each other with a spacer therebetween. Line width of the top of the second gate structure is not less than that of the bottom thereof. A fabrication method thereof is also disclosed. A transient first gate structure and a temporary gate structure are formed by etching through a first hard mask. A second gate structure is formed between a first spacer and a second spacer opposite to each other and disposed respectively on the transient first gate structure and temporary gate structure. The second gate structure is covered with a second hard mask. An etch process is performed through a patterned photoresist layer to remove exposed first hard mask and temporary gate structure and to partially remove exposed portion of first hard mask and transient first gate structure to form the first gate structure.

    Abstract translation: 一种半导体器件，包括彼此紧邻的第一栅极结构和第二栅极结构，其间具有间隔物。 第二栅极结构的顶部的线宽不小于其底部的线宽。 还公开了其制造方法。 通过蚀刻穿过第一硬掩模形成瞬态第一栅极结构和临时栅极结构。 第二栅极结构形成在第一间隔物和彼此相对的第二间隔物之间​​，分别设置在瞬态第一栅极结构和临时栅极结构上。 第二个门结构用第二个硬掩模覆盖。 通过图案化的光致抗蚀剂层进行蚀刻处理以去除暴露的第一硬掩模和临时栅极结构，并且部分地去除第一硬掩模和瞬态第一栅极结构的暴露部分以形成第一栅极结构。

    MANUFACTURING METHOD OF GATE STRUCTURE
    6.
    发明公开
    MANUFACTURING METHOD OF GATE STRUCTURE 审中-公开

    公开(公告)号：US20240063052A1

    公开(公告)日：2024-02-22

    申请号：US17949186

    申请日：2022-09-20

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Tzu-Feng Weng ,  Chao-Sheng Cheng ,  Chi-Cheng Huang

    IPC: H01L21/762 ,  H01L21/28 ,  H01L29/66

    CPC classification number: H01L21/76264 ,  H01L21/28141 ,  H01L29/66545

    Abstract: A manufacturing method of a gate structure includes the following steps. A semiconductor substrate is provided. An isolation structure is formed in the semiconductor substrate and surrounds an active region in the semiconductor substrate. A gate pattern is formed on the active region and the isolation structure. The gate pattern includes a first gate structure and a first capping layer disposed on the first gate structure. A part of the first capping layer located above an interface between the active region and the isolation structure is removed for exposing a part of the first gate structure located above the interface between the active region and the isolation structure. A removing process is performed for reducing a thickness of the part of the first gate structure located above the interface between the active region and the isolation structure.

    Semiconductor device and fabrication method thereof
    8.
    发明授权
    Semiconductor device and fabrication method thereof 有权
    半导体器件及其制造方法

    公开(公告)号：US09331183B2

    公开(公告)日：2016-05-03

    申请号：US13909057

    申请日：2013-06-03

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hsiang-Chen Lee ,  Ping-Chia Shih ,  Chi-Cheng Huang ,  Wan-Fang Chung ,  Yu-Chun Chang ,  Je-Yi Su

    IPC: H01L29/792 ,  H01L29/66 ,  H01L21/28 ,  H01L29/423 ,  H01L27/115

    CPC classification number: H01L29/66833 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/0332 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/42348 ,  H01L29/792 ,  H01L29/7923

    Abstract: A semiconductor device including a first gate structure and a second gate structure immediately adjacent to each other with a spacer therebetween. Line width of the top of the second gate structure is not less than that of the bottom thereof. A fabrication method thereof is also disclosed. A transient first gate structure and a temporary gate structure are formed by etching through a first hard mask. A second gate structure is formed between a first spacer and a second spacer opposite to each other and disposed respectively on the transient first gate structure and temporary gate structure. The second gate structure is covered with a second hard mask. An etch process is performed through a patterned photoresist layer to remove exposed first hard mask and temporary gate structure and to partially remove exposed portion of first hard mask and transient first gate structure to form the first gate structure.

    Abstract translation: 一种半导体器件，包括彼此紧邻的第一栅极结构和第二栅极结构，其间具有间隔物。 第二栅极结构的顶部的线宽不小于其底部的线宽。 还公开了其制造方法。 通过蚀刻穿过第一硬掩模形成瞬态第一栅极结构和临时栅极结构。 第二栅极结构形成在第一间隔物和彼此相对的第二间隔物之间​​，分别设置在瞬态第一栅极结构和临时栅极结构上。 第二个门结构用第二个硬掩模覆盖。 通过图案化的光致抗蚀剂层进行蚀刻处理以去除暴露的第一硬掩模和临时栅极结构，并且部分地去除第一硬掩模和瞬态第一栅极结构的暴露部分以形成第一栅极结构。

    MEMORY CELL AND FABRICATING METHOD OF THE SAME
    9.
    发明申请
    MEMORY CELL AND FABRICATING METHOD OF THE SAME 有权

    公开(公告)号：US20220336606A1

    公开(公告)日：2022-10-20

    申请号：US17853954

    申请日：2022-06-30

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chih-Hao Pan ,  Chi-Cheng Huang ,  Kuo-Lung Li ,  Szu-Ping Wang ,  Po-Hsuan Chen ,  Chao-Sheng Cheng

    IPC: H01L29/423 ,  H01L29/792 ,  H01L21/28 ,  H01L29/66

    Abstract: A memory cell includes a substrate. A first STI and a second STI are embedded within the substrate. The first STI and the second STI extend along a first direction. An active region is disposed on the substrate and between the first STI and the second STI. A control gate is disposed on the substrate and extends along a second direction. The first direction is different from the second direction. A tunneling region is disposed in the active region overlapping the active region. A first trench is embedded within the tunneling region. Two second trenches are respectively embedded within the first STI and the second STI. The control gate fills in the first trench and the second trenches. An electron trapping stack is disposed between the tunneling region and the control gate.

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