中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

34 records (took 0.013 seconds)

    RESISTIVE RANDOM-ACCESS MEMORY (RRAM) DEVICE AND FORMING METHOD THEREOF
    22.
    发明申请
    RESISTIVE RANDOM-ACCESS MEMORY (RRAM) DEVICE AND FORMING METHOD THEREOF 有权

    公开(公告)号：US20220399495A1

    公开(公告)日：2022-12-15

    申请号：US17378795

    申请日：2021-07-19

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wen-Jen Wang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

    IPC: H01L45/00

    Abstract: A RRAM device includes a bottom electrode, a resistive material layer, a high work function layer, a top electrode, a hard mask and high work function sidewall parts. The bottom electrode, the resistive material layer, the high work function layer, the top electrode and the hard mask are sequentially stacked on a substrate. The high work function sidewall parts cover sidewalls of the top electrode and sidewalls of the hard mask, thereby constituting a RRAM cell. A method of forming said RRAM device is also provided.

    RRAM STRUCTURE AND METHOD OF FABRICATING THE SAME
    24.
    发明申请
    RRAM STRUCTURE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20210217813A1

    公开(公告)日：2021-07-15

    申请号：US16794194

    申请日：2020-02-18

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wen-Jen Wang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

    IPC: H01L27/24 ,  H01L45/00

    Abstract: An RRAM structure includes a substrate. The substrate is divided into a memory cell region and a logic device region. A metal plug is disposed within the memory cell region. An RRAM is disposed on and contacts the metal plug. The RRAM includes a top electrode, a variable resistive layer, and a bottom electrode. The variable resistive layer is disposed between the top electrode and the bottom electrode. The variable resistive layer includes a first bottom surface. The bottom electrode includes a first top surface. The first bottom surface and the first top surface are coplanar. The first bottom surface only overlaps and contacts part of the first top surface.

    SEMICONDUCTOR MEMORY DEVICE AND FABRICATION METHOD THEREOF
    25.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND FABRICATION METHOD THEREOF 审中-公开

    公开(公告)号：US20200185399A1

    公开(公告)日：2020-06-11

    申请号：US16792847

    申请日：2020-02-17

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wen-Jen Wang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

    IPC: H01L27/11568 ,  H01L21/28 ,  H01L29/792

    Abstract: A method for fabricating a semiconductor memory device is disclosed. A substrate having a main surface is provided. A memory gate is formed on the main surface of the substrate. The memory has a first sidewall and a second sidewall opposite to the first sidewall. A control gate is formed in proximity to the memory gate. The control gate has a third sidewall directly facing the second sidewall, and a fourth sidewall opposite to the third sidewall. A gap is formed between the second sidewall of the memory gate and the third sidewall of the control gate. A first single spacer structure is formed on the first sidewall of the memory gate and a second single spacer structure on the fourth sidewall of the control gate. A gap-filling layer is formed to fill up the gap.

    RESISTIVE MEMORY STRUCTURE AND MANUFACTURING METHOD THEREOF
    26.
    发明申请
    RESISTIVE MEMORY STRUCTURE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20250017121A1

    公开(公告)日：2025-01-09

    申请号：US18449716

    申请日：2023-08-15

    Applicant: United Microelectronics Corp.

    Inventor： Wen-Jen Wang ,  Yu-Huan Yeh ,  Chuan-Fu Wang

    IPC: H10N70/00 ,  H10B63/00

    Abstract: A resistive memory structure including a substrate, a dielectric layer, a conductive plug, a resistive memory device, a spacer, and a protective layer is provided. The dielectric layer is located on the substrate. The conductive plug is located in the dielectric layer. The conductive plug has a protrusion portion located outside the dielectric layer. The resistive memory device is located on the conductive plug. The resistive memory device includes a first electrode, a variable resistance layer, and a second electrode. The first electrode is located on the conductive plug. The variable resistance layer is located on the first electrode. The second electrode is located on the variable resistance layer. The spacer is located on a sidewall of the resistive memory device. The protective layer is located on a sidewall of the protrusion portion and between the first electrode and the dielectric layer.

    RESISTIVE SWITCHING DEVICE AND FABRICATION METHOD THEREOF
    27.
    发明申请
    RESISTIVE SWITCHING DEVICE AND FABRICATION METHOD THEREOF 有权

    公开(公告)号：US20240407274A1

    公开(公告)日：2024-12-05

    申请号：US18219717

    申请日：2023-07-10

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wen-Jen Wang ,  Yu-Huan Yeh ,  Chuan-Fu Wang

    IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

    Abstract: A resistive switching device includes a substrate; a first dielectric layer on the substrate; a conductive via in the first dielectric layer; a bottom electrode on the conductive via and the first dielectric layer, a resistive switching layer on the bottom electrode; and a cone-shaped top electrode on the resistive switching layer. The cone-shaped top electrode can produce increased and concentrated electric field during operation, which facilitates the filament forming process.

    RESISTIVE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
    28.
    发明申请
    RESISTIVE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20240407273A1

    公开(公告)日：2024-12-05

    申请号：US18218602

    申请日：2023-07-06

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wen-Jen Wang ,  Hsiang-Hung Peng ,  Yu-Huan Yeh ,  Chuan-Fu Wang

    IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

    Abstract: A resistive memory device includes a first dielectric layer, a via connection structure, and a resistive switching element. The via connection structure is disposed in the first dielectric layer, and the resistive switching element is disposed on the via connection structure and the first dielectric layer. The resistive switching element includes a titanium bottom electrode, a titanium top electrode, and a variable resistance material. The titanium top electrode is disposed above the titanium bottom electrode, and the variable resistance material is sandwiched between the titanium bottom electrode and the titanium top electrode in a vertical direction. The variable resistance material is directly connected with the titanium bottom electrode and the titanium top electrode, and the titanium bottom electrode is directly connected with the via connection structure.

    RESISTIVE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
    30.
    发明公开
    RESISTIVE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20240107902A1

    公开(公告)日：2024-03-28

    申请号：US17970560

    申请日：2022-10-20

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wen-Jen Wang ,  Yu-Huan Yeh ,  Chuan-Fu Wang

    IPC: H01L45/00 ,  H01L23/48 ,  H01L27/24

    CPC classification number: H01L45/1253 ,  H01L23/481 ,  H01L27/24 ,  H01L45/1666

    Abstract: A resistive memory device includes a dielectric layer, a via connection structure, a stacked structure, and an insulating structure. The via connection structure is disposed in the dielectric layer. The stacked structure is disposed on the via connection structure and the dielectric layer. The insulating structure penetrates through the stacked structure in a vertical direction and divides the stacked structure into a first memory cell unit and a second memory cell unit. The first memory cell unit includes a first bottom electrode, and the second memory cell unit includes a second bottom electrode separated from the first bottom electrode by the insulating structure. The via connection structure is electrically connected with the first bottom electrode and the second bottom electrode.

Patent Agency Ranking