Constrained coefficient adaptation for continuous-time equalizers
    24.
    发明授权
    Constrained coefficient adaptation for continuous-time equalizers 有权
    连续时间均衡器的约束系数适应

    公开(公告)号:US07053688B2

    公开(公告)日:2006-05-30

    申请号:US10970471

    申请日:2004-10-20

    IPC分类号: G06G7/16

    CPC分类号: H04L25/03885

    摘要: A low-voltage constrained coefficient adaptation and multiplication is provided. To provide the constrained coefficient adaptation, an adder adds an adaptive differential control voltage to a forcing differential control voltage to provide an effective coefficient. The adder is configured such that the forcing differential control voltage can prevent the adaptive differential control voltage from producing a sign change in the effective coefficient.

    摘要翻译: 提供了低压约束系数适应和乘法。 为了提供约束系数自适应,加法器将自适应差分控制电压加到强制差分控制电压以提供有效系数。 加法器被配置为使得强制差分控制电压可以防止自适应差分控制电压产生有效系数的符号变化。

    CONSTRAINED COEFFICIENT ADAPTATION FOR CONTINUOUS-TIME EQUALIZERS
    29.
    发明申请
    CONSTRAINED COEFFICIENT ADAPTATION FOR CONTINUOUS-TIME EQUALIZERS 有权
    对连续均衡器的约束系数适应

    公开(公告)号:US20060082406A1

    公开(公告)日:2006-04-20

    申请号:US10970471

    申请日:2004-10-20

    IPC分类号: G06F7/44

    CPC分类号: H04L25/03885

    摘要: A low-voltage constrained coefficient adaptation and multiplication is provided. To provide the constrained coefficient adaptation, an adder adds an adaptive differential control voltage to a forcing differential control voltage to provide an effective coefficient. The adder is configured such that the forcing differential control voltage can prevent the adaptive differential control voltage from producing a sign change in the effective coefficient.

    摘要翻译: 提供了低压约束系数适应和乘法。 为了提供约束系数自适应,加法器将自适应差分控制电压加到强制差分控制电压以提供有效系数。 加法器被配置为使得强制差分控制电压可以防止自适应差分控制电压产生有效系数的符号变化。

    Analog signal interpolation
    30.
    发明申请
    Analog signal interpolation 有权
    模拟信号插补

    公开(公告)号:US20060044167A1

    公开(公告)日:2006-03-02

    申请号:US11209010

    申请日:2005-08-22

    IPC分类号: H03M3/00

    CPC分类号: G06G7/30 H03F3/45183

    摘要: A linear interpolator is provided that includes differential pairs of transistors biased such that a first input voltage may be multiplied by a factor r wherein 0≦r≦1 and such that a second input voltage may be multiplied by the complement factor (1−r). By combining the multiplied input voltages, a linear interpolation is provided based upon the factor r.

    摘要翻译: 提供了线性内插器,其包括被偏置的差分对晶体管,使得第一输入电压可以乘以因子r,其中0≤r≤1,并且使得第二输入电压可以乘以补码因子(1- r)。 通过组合倍增的输入电压,基于因子r提供线性内插。