公开(公告)号：US20060259669A1

公开(公告)日：2006-11-16

申请号：US11128135

申请日：2005-05-11

申请人： Kenneth Alan Dockser ,  Victor Roberts Augsburg ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Robert Douglas Clancy ,  Thomas Andrew Sartorius

发明人： Kenneth Alan Dockser ,  Victor Roberts Augsburg ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Robert Douglas Clancy ,  Thomas Andrew Sartorius

IPC分类号： G06F13/38

CPC分类号： G06F13/4059 ,  G06F5/06 ,  G06F2205/126

摘要： Data from a source domain operating at a first data rate is transferred to a FIFO in another domain operating at a different data rate. The FIFO buffers data before transfer to a sink for further processing or storage. A source side counter tracks space available in the FIFO. In disclosed examples, the initial counter value corresponds to FIFO depth. The counter decrements in response to a data ready signal from the source domain, without delay. The counter increments in response to signaling from the sink domain of a read of data off the FIFO. Hence, incrementing is subject to the signaling latency between domains. The source may send one more beat of data when the counter indicates the FIFO is full. The last beat of data is continuously sent from the source until it is indicated that a FIFO position became available; effectively providing one more FIFO position.

摘要翻译： 来自以第一数据速率运行的源域的数据被传送到以不同数据速率工作的另一个域中的FIFO。 FIFO在传输到宿之前缓冲数据以进一步处理或存储。 源端计数器跟踪FIFO中可用的空间。 在公开的示例中，初始计数器值对应于FIFO深度。 响应于来自源域的数据就绪信号，计数器无延迟地递减。 响应于来自接收器域的信令从FIFO读取数据，计数器递增。 因此，增量受到域之间的信令等待时间的限制。 当计数器指示FIFO已满时，源可能再发送一次数据。 数据的最后一次节拍从源头连续发送到指示FIFO位置可用为止; 有效提供一个FIFO位置。

公开(公告)号：US07210024B2

公开(公告)日：2007-04-24

申请号：US11055919

申请日：2005-02-10

申请人： Michael Scott McIlvaine ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith

发明人： Michael Scott McIlvaine ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith

IPC分类号： G06F9/30

CPC分类号： G06F9/3867 ,  G06F9/30072 ,  G06F9/3017 ,  G06F9/30181 ,  G06F9/3824 ,  G06F9/3826

摘要： Hazard detection is simplified by converting a conditional instruction, operative to perform an operation if a condition is satisfied, into an emissary instruction operative to evaluate the condition and an unconditional base instruction operative to perform the operation. The emissary instruction is executed, while the base instruction is halted. The emissary instruction evaluates the condition and reports the condition evaluation back to the base instruction. Based on the condition evaluation, the base instruction is either launched into the pipeline for execution, or it is discarded (or a NOP, or null instruction, substituted for it). In either case, the dependencies of following instructions may be resolved.

摘要翻译： 通过转换条件指令来简化危险检测，条件指令可操作以在满足条件的情况下执行操作到可操作以评估条件的执行指令和用于执行操作的无条件基准指令。 在基本指令停止的情况下执行执行指令。 使者指令评估条件并将条件评估报告回基本指令。 基于条件评估，基本指令要么被启动到管道中才能执行，要么被丢弃（或者一个NOP或者空的指令代替它）。 在任一情况下，可以解决以下指令的依赖性。

公开(公告)号：US07404042B2

公开(公告)日：2008-07-22

申请号：US11132749

申请日：2005-05-18

申请人： Brian Michael Stempel ,  Jeffrey Todd Bridges ,  Rodney Wayne Smith ,  Thomas Andrew Sartorius

发明人： Brian Michael Stempel ,  Jeffrey Todd Bridges ,  Rodney Wayne Smith ,  Thomas Andrew Sartorius

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F9/30149 ,  G06F9/30047 ,  G06F9/30181 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3816 ,  G06F9/3875 ,  G06F12/0875 ,  G06F12/0886 ,  G06F2212/655

摘要： A fetch section of a processor comprises an instruction cache and a pipeline of several stages for obtaining instructions. Instructions may cross cache line boundaries. The pipeline stages process two addresses to recover a complete boundary crossing instruction. During such processing, if the second piece of the instruction is not in the cache, the fetch with regard to the first line is invalidated and recycled. On this first pass, processing of the address for the second part of the instruction is treated as a pre-fetch request to load instruction data to the cache from higher level memory, without passing any of that data to the later stages of the processor. When the first line address passes through the fetch stages again, the second line address follows in the normal order, and both pieces of the instruction are can be fetched from the cache and combined in the normal manner.

摘要翻译： 处理器的获取部分包括指令高速缓存和用于获取指令的若干级的流水线。 指令可能会跨越缓存行边界。 流水线处理两个地址以恢复完整的边界交叉指令。 在这种处理过程中，如果第二条指令不在高速缓存中，则关于第一行的提取将被无效再循环。 在该第一遍中，对于指令的第二部分的地址的处理被视为从高级存储器将指令数据加载到高速缓存的预取请求，而不将该数据传递到处理器的后期。 当第一行地址再次通过读取级时，第二行地址以正常顺序跟随，并且可以从高速缓存中取出两条指令并以正常方式进行组合。

公开(公告)号：US07568070B2

公开(公告)日：2009-07-28

申请号：US11193547

申请日：2005-07-29

申请人： Jeffrey Todd Bridges ,  James Norris Dieffenderfer ,  Rodney Wayne Smith ,  Thomas Andrew Sartorius

发明人： Jeffrey Todd Bridges ,  James Norris Dieffenderfer ,  Rodney Wayne Smith ,  Thomas Andrew Sartorius

IPC分类号： G06F9/34

CPC分类号： G06F9/30149 ,  G06F9/3816 ,  G06F9/382

摘要： A fixed number of variable-length instructions are stored in each line of an instruction cache. The variable-length instructions are aligned along predetermined boundaries. Since the length of each instruction in the line, and hence the span of memory the instructions occupy, is not known, the address of the next following instruction is calculated and stored with the cache line. Ascertaining the instruction boundaries, aligning the instructions, and calculating the next fetch address are performed in a predecoder prior to placing the instructions in the cache.

摘要翻译： 固定数量的可变长度指令存储在指令高速缓存的每一行中。 可变长度指令沿预定边界排列。 由于行中的每条指令的长度以及指令占用的存储器的跨度是未知的，所以下一个跟随指令的地址被计算并与高速缓存行一起存储。 在将指令置于高速缓存之前，确定指令边界，对准指令并计算下一个提取地址在预解码器中执行。

公开(公告)号：US07415638B2

公开(公告)日：2008-08-19

申请号：US10995858

申请日：2004-11-22

申请人： Rodney Wayne Smith ,  Brian Michael Stempel ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Thomas Andrew Sartorius

发明人： Rodney Wayne Smith ,  Brian Michael Stempel ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Thomas Andrew Sartorius

IPC分类号： G06F11/00 ,  G06F9/30

CPC分类号： G06F9/3861 ,  G06F9/30152 ,  G06F9/3017 ,  G06F9/382

摘要： In a pipelined processor where instructions are pre-decoded prior to being stored in a cache, an incorrectly pre-decoded instruction is detected during execution in the pipeline. The corresponding instruction is invalidated in the cache, and the instruction is forced to evaluate as a branch instruction. In particular, the branch instruction is evaluated as “mispredicted not taken” with a branch target address of the incorrectly pre-decoded instruction's address. This, with the invalidated cache line, causes the incorrectly pre-decoded instruction to be re-fetched from memory with a precise address. The re-fetched instruction is then correctly pre-decoded, written to the cache, and executed.

摘要翻译： 在流水线处理器中，在将存储在高速缓存中的指令进行预解码之前，在流水线执行期间检测到未正确预解码的指令。 相应的指令在缓存中无效，并且强制将该指令作为分支指令进行求值。 特别地，分支指令被评估为未被错误地预解码的指令的地址的分支目标地址“未被采用”。 这使得无效的高速缓存行导致错误地预解码的指令从具有精确地址的存储器重新获取。 然后重新获取的指令被正确预解码，写入高速缓存并执行。

公开(公告)号：US07278012B2

公开(公告)日：2007-10-02

申请号：US11144206

申请日：2005-06-02

申请人： Thomas Andrew Sartorius ,  Brian Michael Stempel ,  Jeffrey Todd Bridges ,  James Norris Dieffenderfer ,  Rodney Wayne Smith

发明人： Thomas Andrew Sartorius ,  Brian Michael Stempel ,  Jeffrey Todd Bridges ,  James Norris Dieffenderfer ,  Rodney Wayne Smith

IPC分类号： G06F9/42

CPC分类号： G06F9/3844

摘要： A microprocessor includes two branch history tables, and is configured to use a first one of the branch history tables for predicting branch instructions that are hits in a branch target cache, and to use a second one of the branch history tables for predicting branch instructions that are misses in the branch target cache. As such, the first branch history table is configured to have an access speed matched to that of the branch target cache, so that its prediction information is timely available relative to branch target cache hit detection, which may happen early in the microprocessor's instruction pipeline. The second branch history table thus need only be as fast as is required for providing timely prediction information in association with recognizing branch target cache misses as branch instructions, such as at the instruction decode stage(s) of the instruction pipeline.

摘要翻译： 微处理器包括两个分支历史表，并且被配置为使用第一个分支历史表来预测分支目标高速缓存中的命中的分支指令，并且使用第二个分支历史表来预测分支指令， 在分支目标缓存中丢失。 因此，第一分支历史表被配置为具有与分支目标高速缓存的访问速度匹配的访问速度，使得其预测信息相对于可能在微处理器的指令流水线的早期发生的分支目标高速缓存命中检测而及时可用。 因此，第二分支历史表仅需要与将识别分支目标高速缓存未命中作为分支指令（例如在指令流水线的指令解码阶段）相关联地提供及时的预测信息所需的速度。

公开(公告)号：US07203826B2

公开(公告)日：2007-04-10

申请号：US11061975

申请日：2005-02-18

申请人： Rodney Wayne Smith ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Thomas Andrew Sartorius

发明人： Rodney Wayne Smith ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Thomas Andrew Sartorius

IPC分类号： G06F9/38

CPC分类号： G06F9/3806 ,  G06F9/30054 ,  G06F9/4486

摘要： A processor includes a return stack circuit used for predicting procedure return addresses for instruction pre-fetching, wherein a return stack controller determines the number of return levels associated with a given return instruction, and pops that number of return addresses from the return stack. Popping multiple return addresses from the return stack permits the processor to pre-fetch the return address of the original calling procedure in a chain of successive procedure calls. In one embodiment, the return stack controller reads the number of return levels from a value embedded in the return instruction. A complementary compiler calculates the return level values for given return instructions and embeds those values in them at compile-time. In another embodiment, the return stack circuit dynamically tracks the number of return levels by counting the procedure calls (branches) in a chain of successive procedure calls.

摘要翻译： 处理器包括用于预测用于指令预取的过程返回地址的返回堆栈电路，其中返回堆栈控制器确定与给定返回指令相关联的返回电平的数量，并且从返回堆栈中弹出该返回地址的数量。 从返回堆栈弹出多个返回地址允许处理器在连续的过程调用链中预取原始调用过程的返回地址。 在一个实施例中，返回堆栈控制器从嵌入在返回指令中的值读取返回电平的数量。 补充编译器计算给定返回指令的返回值，并在编译时嵌入这些值。 在另一个实施例中，返回堆栈电路通过对连续过程调用链中的过程调用（分支）进行计数来动态地跟踪返回电平的数量。

公开(公告)号：US07376815B2

公开(公告)日：2008-05-20

申请号：US11066957

申请日：2005-02-25

申请人： Rodney Wayne Smith ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Thomas Andrew Sartorius

发明人： Rodney Wayne Smith ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Thomas Andrew Sartorius

IPC分类号： G06F9/30

CPC分类号： G06F9/30149 ,  G06F8/447 ,  G06F9/382

摘要： Techniques for ensuring a synchronized predecoding of an instruction string are disclosed. The instruction string contains instructions from a variable length instruction set and embedded data. One technique includes defining a granule to be equal to the smallest length instruction in the instruction set and defining the number of granules that compose the longest length instruction in the instruction set to be MAX. The technique further includes determining the end of an embedded data segment, when a program is compiled or assembled into the instruction string and inserting a padding of length, MAX−1, into the instruction string to the end of the embedded data. Upon predecoding of the padded instruction string, a predecoder maintains synchronization with the instructions in the padded instruction string even if embedded data is coincidentally encoded to resemble an existing instruction in the variable length instruction set.

摘要翻译： 公开了用于确保指令串的同步预解码的技术。 指令串包含来自可变长度指令集和嵌入数据的指令。 一种技术包括定义一个等于指令集中最小长度指令的粒子，并将构成指令集中最长指令的粒子数定义为MAX。 该技术还包括当程序被编译或组装成指令串并将长度为MAX-1的填充插入到嵌入数据的结尾的指令串中时，确定嵌入数据段的结束。 在预编译填充指令串时，即使嵌入数据被巧合地编码成类似于可变长度指令集中的现有指令，预解码器也保持与填充指令串中的指令的同步。

公开(公告)号：US07624256B2

公开(公告)日：2009-11-24

申请号：US11106803

申请日：2005-04-14

申请人： Thomas Andrew Sartorius ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Kenneth Alan Dockser ,  Michael Scott McIlvaine ,  Rodney Wayne Smith

发明人： Thomas Andrew Sartorius ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Kenneth Alan Dockser ,  Michael Scott McIlvaine ,  Rodney Wayne Smith

IPC分类号： G06F13/00

CPC分类号： G06F9/30072 ,  G06F9/3826 ,  G06F9/3838 ,  G06F9/384

摘要： A conditional instruction architected to receive one or more operands as inputs, to output to a target the result of an operation performed on the operands if a condition is satisfied, and to not provide an output if the condition is not satisfied, is executed so that it unconditionally provides an output to the target. The conditional instruction obtains the prior value of the target (that is, the value produced by the most recent instruction preceding the conditional instruction that updated that target). The condition is evaluated. If the condition is satisfied, an operation is performed and the result of the operation output to the target. If the condition is not satisfied, the prior value is output to the target. Subsequent instructions may rely on the target as an operand source (whether written to a register or forwarded to the instruction), prior to the condition evaluation.

摘要翻译： 一种条件指令，被设计为接收一个或多个操作数作为输入，如果满足条件，则向目标输出对操作数执行的操作的结果，并且如果条件不满足则不提供输出，以便 它无条件地向目标提供输出。 条件指令获取目标的先前值（即由更新该目标的条件指令之前的最新指令产生的值）。 评估条件。 如果满足条件，则执行操作并将操作结果输出到目标。 如果条件不满足，则将先前值输出到目标。 后续指令可以在条件评估之前依赖目标作为操作数源（无论是写入寄存器还是转发到指令）。

公开(公告)号：US07421568B2

公开(公告)日：2008-09-02

申请号：US11073284

申请日：2005-03-04

申请人： Brian Michael Stempel ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Rodney Wayne Smith ,  Thomas Andrew Sartorius

发明人： Brian Michael Stempel ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Rodney Wayne Smith ,  Thomas Andrew Sartorius

IPC分类号： G06F9/30

CPC分类号： G06F9/382 ,  G06F9/30152 ,  G06F9/3816 ,  G06F12/0875 ,  Y02D10/13

摘要： A processor capable of fetching and executing variable length instructions is described having instructions of at least two lengths. The processor operates in multiple modes. One of the modes restricts instructions that can be fetched and executed to the longer length instructions. An instruction cache is used for storing variable length instructions and their associated predecode bit fields in an instruction cache line and storing the instruction address and processor operating mode state information at the time of the fetch in a tag line. The processor operating mode state information indicates the program specified mode of operation of the processor. The processor fetches instructions from the instruction cache for execution. As a result of an instruction fetch operation, the instruction cache may selectively enable the writing of predecode bit fields in the instruction cache and may selectively enable the reading of predecode bit fields stored in the instruction cache based on the processor state at the time of the fetch.

摘要翻译： 描述具有至少两个长度的指令的能够获取和执行可变长度指令的处理器。 处理器以多种模式运行。 其中一种模式限制了可以获取并执行到较长长度指令的指令。 指令高速缓存用于在指令高速缓存行中存储可变长度指令及其相关联的预解码位字段，并且在获取标签行时存储指令地址和处理器操作模式状态信息。 处理器操作模式状态信息指示处理器的程序指定的操作模式。 处理器从指令缓存器中获取指令以执行。 作为指令提取操作的结果，指令高速缓存可以选择性地启用指令高速缓存中的预解码位字段的写入，并且可以基于处理器状态来选择性地启用存储在指令高速缓存中的预解码位字段的读取 取。