公开(公告)号：US20080239860A1

公开(公告)日：2008-10-02

申请号：US12134537

申请日：2008-06-06

申请人： Sam Gat-Shang Chu ,  Maureen Anne Delaney ,  Saiful Islam ,  Dung Quoc Nguyen ,  Jafar Nahidi

发明人： Sam Gat-Shang Chu ,  Maureen Anne Delaney ,  Saiful Islam ,  Dung Quoc Nguyen ,  Jafar Nahidi

IPC分类号： G11C8/00

CPC分类号： G06F9/30141

摘要： An apparatus and method are provided for reading a plurality of consecutive entries and writing a plurality of consecutive entries with only one read address and one write address using a 2Read/2Write register file. In one exemplary embodiment, a 64 entry register file array is partitioned into four sub-arrays. Each sub-array contains sixteen entries having one or more 2Read/2Write SRAM cells. The apparatus and method provide a mechanism to write the consecutive entries by only having a 4 to 16 decode of one address. In addition, the apparatus and method provide a mechanism for reading data from the register file array using a starting read word address and two read word lines generated based on the starting read word address. The two read word lines are used to access the two read ports of the entries in the sub-arrays.

摘要翻译： 提供一种用于读取多个连续条目并使用2Read / 2Write寄存器文件仅写入一个读取地址和一个写入地址的多个连续条目的装置和方法。 在一个示例性实施例中，64个入口寄存器文件阵列被划分为四个子阵列。 每个子阵列包含16个具有一个或多个2Read / 2Write SRAM单元的条目。 该装置和方法提供了通过仅对一个地址进行4到16个解码来写入连续条目的机制。 此外，该装置和方法提供了一种用于使用起始读字地址和基于起始读字地址生成的两个读字线从寄存器堆数组读取数据的机制。 两条读字线用于访问子阵列中条目的两个读端口。

公开(公告)号：US07243170B2

公开(公告)日：2007-07-10

申请号：US10707149

申请日：2003-11-24

申请人： Taqi N. Buti ,  Brian W. Curran ,  Maureen A. Delaney ,  Saiful Islam ,  Zakaria M. Khwaja ,  Jafar Nahidi ,  Dung Q. Nguyen

发明人： Taqi N. Buti ,  Brian W. Curran ,  Maureen A. Delaney ,  Saiful Islam ,  Zakaria M. Khwaja ,  Jafar Nahidi ,  Dung Q. Nguyen

IPC分类号： G06F3/00 ,  G06F5/00

CPC分类号： G06F9/3802 ,  G06F9/3814

摘要： An instruction buffer and a method of buffering instructions. The instruction buffer including: a memory array partitioned into multiple identical memory sub-arrays arranged in sequential order from a first memory sub-array to a last memory sub-array, each memory sub-array having multiple instruction entry positions and adapted to store a different instruction of a set of concurrent instructions in a single instruction entry position of any one of the memory sub-arrays, the set of concurrent instructions arranged in sequential order from a first instruction to a last instruction

摘要翻译： 指令缓冲器和缓冲指令的方法。 所述指令缓冲器包括：分割成从第一存储器子阵列到最后存储器子阵列的顺序排列的多个相同的存储器子阵列的存储器阵列，每个存储器子阵列具有多个指令条目位置，并且适于存储 任何一个存储器子阵列的单个指令输入位置中的一组并行指令的不同指令，以从第一指令到最后指令的顺序排列的并发指令集

公开(公告)号：US20050216698A1

公开(公告)日：2005-09-29

申请号：US10798902

申请日：2004-03-11

申请人： Sam Chu ,  Saiful Islam ,  Shelton Leung ,  Jose Paredes

发明人： Sam Chu ,  Saiful Islam ,  Shelton Leung ,  Jose Paredes

IPC分类号： G06F9/30 ,  G06F15/00

CPC分类号： G06F9/30141

摘要： A register file is often used within integrated circuitry to temporarily hold data. Sometimes this data needs to be retained within the register file for a period of time, such as when there is a stall operation. Conventional register files have utilized a hold multiplexor to perform such a stall operation. The multiplexor however inserts a delay that is undesirable in high performance integrated circuitry. The multiplexor is replaced with a tri-state inverter coupled to the global bit line of the register file, which minimizes this additional delay from the register file data access time.

摘要翻译： 集成电路中经常使用寄存器文件来临时保存数据。 有时，这些数据需要在寄存器文件中保留一段时间，例如当有停机操作时。 传统的寄存器文件已经使用保持多路复用器来执行这种失速操作。 然而，多路复用器插入在高性能集成电路中不期望的延迟。 多路复用器被替换为耦合到寄存器堆的全局位线的三态反相器，这使得从寄存器文件数据访问时间的这个附加延迟最小化。