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    Method and circuit for reading and writing an instruction buffer
    1.
    发明授权
    Method and circuit for reading and writing an instruction buffer 有权
    用于读写指令缓冲器的方法和电路

    公开(公告)号：US07243170B2

    公开(公告)日：2007-07-10

    申请号：US10707149

    申请日：2003-11-24

    申请人： Taqi N. Buti ,  Brian W. Curran ,  Maureen A. Delaney ,  Saiful Islam ,  Zakaria M. Khwaja ,  Jafar Nahidi ,  Dung Q. Nguyen

    发明人： Taqi N. Buti ,  Brian W. Curran ,  Maureen A. Delaney ,  Saiful Islam ,  Zakaria M. Khwaja ,  Jafar Nahidi ,  Dung Q. Nguyen

    IPC分类号： G06F3/00 ,  G06F5/00

    CPC分类号： G06F9/3802 ,  G06F9/3814

    摘要： An instruction buffer and a method of buffering instructions. The instruction buffer including: a memory array partitioned into multiple identical memory sub-arrays arranged in sequential order from a first memory sub-array to a last memory sub-array, each memory sub-array having multiple instruction entry positions and adapted to store a different instruction of a set of concurrent instructions in a single instruction entry position of any one of the memory sub-arrays, the set of concurrent instructions arranged in sequential order from a first instruction to a last instruction

    摘要翻译： 指令缓冲器和缓冲指令的方法。 所述指令缓冲器包括：分割成从第一存储器子阵列到最后存储器子阵列的顺序排列的多个相同的存储器子阵列的存储器阵列，每个存储器子阵列具有多个指令条目位置，并且适于存储 任何一个存储器子阵列的单个指令输入位置中的一组并行指令的不同指令，以从第一指令到最后指令的顺序排列的并发指令集

    Dependency matrix with reduced area and power consumption
    2.
    发明授权
    Dependency matrix with reduced area and power consumption 失效
    具有减少面积和功耗的依赖矩阵

    公开(公告)号：US08127116B2

    公开(公告)日：2012-02-28

    申请号：US12417768

    申请日：2009-04-03

    申请人： Saiful Islam ,  Mary D. Brown ,  Bjorn P. Christensen ,  Sam G. Chu ,  Robert A. Cordes ,  Maureen A. Delaney ,  Jafar Nahidi ,  Joel A. Silberman

    发明人： Saiful Islam ,  Mary D. Brown ,  Bjorn P. Christensen ,  Sam G. Chu ,  Robert A. Cordes ,  Maureen A. Delaney ,  Jafar Nahidi ,  Joel A. Silberman

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3838

    摘要： A processor having a dependency matrix comprises a first array comprising a plurality of first cells. A second array couples to the first array and comprises a plurality of second cells. A first write port couples to the first array and the second array and writes to the first array and the second array. A first read port couples to the first array and the second array and reads from the first array and the second array. A second read port couples to the first array and reads from the first array. A second write port couples to the second read port, reads from the second read port and writes to the second array.

    摘要翻译： 具有依赖矩阵的处理器包括包括多个第一单元的第一阵列。 第二阵列耦合到第一阵列并且包括多个第二单元。 第一个写入端口耦合到第一个阵列和第二个阵列，并写入第一个阵列和第二个阵列。 第一读端口耦合到第一阵列和第二阵列，并从第一阵列和第二阵列读取。 第二个读取端口耦合到第一个数组并从第一个数组读取。 第二个写入端口耦合到第二个读取端口，从第二个读取端口读取并写入第二个数据。

    Dependency Matrix with Reduced Area and Power Consumption
    3.
    发明申请
    Dependency Matrix with Reduced Area and Power Consumption 失效
    具有减小面积和功耗的依赖矩阵

    公开(公告)号：US20100257336A1

    公开(公告)日：2010-10-07

    申请号：US12417768

    申请日：2009-04-03

    申请人： Saiful Islam ,  Mary D. Brown ,  Bjorn P. Christensen ,  Sam G. Chu ,  Robert A. Cordes ,  Maureen A. Delaney ,  Jafar Nahidi ,  Joel A. Silberman

    发明人： Saiful Islam ,  Mary D. Brown ,  Bjorn P. Christensen ,  Sam G. Chu ,  Robert A. Cordes ,  Maureen A. Delaney ,  Jafar Nahidi ,  Joel A. Silberman

    IPC分类号： G06F9/44 ,  G06F15/00 ,  G06F9/30

    CPC分类号： G06F9/3838

    摘要： A processor having a dependency matrix comprises a first array comprising a plurality of first cells. A second array couples to the first array and comprises a plurality of second cells. A first write port couples to the first array and the second array and writes to the first array and the second array. A first read port couples to the first array and the second array and reads from the first array and the second array. A second read port couples to the first array and reads from the first array. A second write port couples to the second read port, reads from the second read port and writes to the second array.

    摘要翻译： 具有依赖矩阵的处理器包括包括多个第一单元的第一阵列。 第二阵列耦合到第一阵列并且包括多个第二单元。 第一个写入端口耦合到第一个阵列和第二个阵列，并写入第一个阵列和第二个阵列。 第一读端口耦合到第一阵列和第二阵列，并从第一阵列和第二阵列读取。 第二个读取端口耦合到第一个数组并从第一个数组读取。 第二个写入端口耦合到第二个读取端口，从第二个读取端口读取并写入第二个数据。

    Method and system for speculatively issuing instructions
    4.
    发明授权
    Method and system for speculatively issuing instructions 失效
    推测发布指令的方法和系统

    公开(公告)号：US06535973B1

    公开(公告)日：2003-03-18

    申请号：US09383606

    申请日：1999-08-26

    申请人： Hoichi Cheong ,  Maureen A. Delaney ,  Hung Qui Le ,  Robert McDonald ,  Dung Quoc Nguyen ,  David Wayne Victor

    发明人： Hoichi Cheong ,  Maureen A. Delaney ,  Hung Qui Le ,  Robert McDonald ,  Dung Quoc Nguyen ,  David Wayne Victor

    IPC分类号： G06F9312

    CPC分类号： G06F9/3861 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384

    摘要： A method and system for speculatively issuing instructions which are dependent upon results from execution of other instructions. Instructions are speculatively issued, dependent upon a result from execution of a primary instruction, wherein the speculatively issued instructions are issued after execution of the primary instruction. N clock cycles are tracked after execution of the primary instruction, wherein the result from execution of said primary instruction is expected within n clock cycles. Execution of any speculatively issued instructions which are dependent upon the primary instruction is cancelled if the result is not returned from execution of the primary instruction within n clock cycles, such that for primary instructions for which the result is returned within the expected n clock cycles any speculatively issued instructions dependent upon said result are executed with increased efficiency.

    摘要翻译： 用于推测发出指令的方法和系统，其依赖于执行其他指令的结果。 根据执行主指令的结果推测发出指令，其中在执行主指令之后发出推测发出的指令。 在执行主指令之后追踪N个时钟周期，其中预期在n个时钟周期内执行所述主指令的结果。 如果在n个时钟周期内没有从主指令的执行中返回结果，则取消依赖于主指令的任何推测发出的指令的执行，使得对于在预期的n个时钟周期内返回结果的主指令， 推测发出依赖于所述结果的指令以更高的效率执行。