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公开(公告)号：US07243170B2
公开(公告)日：2007-07-10
申请号：US10707149
申请日：2003-11-24
申请人： Taqi N. Buti , Brian W. Curran , Maureen A. Delaney , Saiful Islam , Zakaria M. Khwaja , Jafar Nahidi , Dung Q. Nguyen
发明人： Taqi N. Buti , Brian W. Curran , Maureen A. Delaney , Saiful Islam , Zakaria M. Khwaja , Jafar Nahidi , Dung Q. Nguyen
CPC分类号： G06F9/3802 , G06F9/3814
摘要： An instruction buffer and a method of buffering instructions. The instruction buffer including: a memory array partitioned into multiple identical memory sub-arrays arranged in sequential order from a first memory sub-array to a last memory sub-array, each memory sub-array having multiple instruction entry positions and adapted to store a different instruction of a set of concurrent instructions in a single instruction entry position of any one of the memory sub-arrays, the set of concurrent instructions arranged in sequential order from a first instruction to a last instruction
摘要翻译： 指令缓冲器和缓冲指令的方法。 所述指令缓冲器包括：分割成从第一存储器子阵列到最后存储器子阵列的顺序排列的多个相同的存储器子阵列的存储器阵列，每个存储器子阵列具有多个指令条目位置，并且适于存储 任何一个存储器子阵列的单个指令输入位置中的一组并行指令的不同指令，以从第一指令到最后指令的顺序排列的并发指令集
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公开(公告)号：US08127116B2
公开(公告)日：2012-02-28
申请号：US12417768
申请日：2009-04-03
申请人： Saiful Islam , Mary D. Brown , Bjorn P. Christensen , Sam G. Chu , Robert A. Cordes , Maureen A. Delaney , Jafar Nahidi , Joel A. Silberman
发明人： Saiful Islam , Mary D. Brown , Bjorn P. Christensen , Sam G. Chu , Robert A. Cordes , Maureen A. Delaney , Jafar Nahidi , Joel A. Silberman
IPC分类号： G06F9/30
CPC分类号： G06F9/3838
摘要： A processor having a dependency matrix comprises a first array comprising a plurality of first cells. A second array couples to the first array and comprises a plurality of second cells. A first write port couples to the first array and the second array and writes to the first array and the second array. A first read port couples to the first array and the second array and reads from the first array and the second array. A second read port couples to the first array and reads from the first array. A second write port couples to the second read port, reads from the second read port and writes to the second array.
摘要翻译： 具有依赖矩阵的处理器包括包括多个第一单元的第一阵列。 第二阵列耦合到第一阵列并且包括多个第二单元。 第一个写入端口耦合到第一个阵列和第二个阵列，并写入第一个阵列和第二个阵列。 第一读端口耦合到第一阵列和第二阵列，并从第一阵列和第二阵列读取。 第二个读取端口耦合到第一个数组并从第一个数组读取。 第二个写入端口耦合到第二个读取端口，从第二个读取端口读取并写入第二个数据。
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公开(公告)号：US20100257336A1
公开(公告)日：2010-10-07
申请号：US12417768
申请日：2009-04-03
申请人： Saiful Islam , Mary D. Brown , Bjorn P. Christensen , Sam G. Chu , Robert A. Cordes , Maureen A. Delaney , Jafar Nahidi , Joel A. Silberman
发明人： Saiful Islam , Mary D. Brown , Bjorn P. Christensen , Sam G. Chu , Robert A. Cordes , Maureen A. Delaney , Jafar Nahidi , Joel A. Silberman
CPC分类号： G06F9/3838
摘要： A processor having a dependency matrix comprises a first array comprising a plurality of first cells. A second array couples to the first array and comprises a plurality of second cells. A first write port couples to the first array and the second array and writes to the first array and the second array. A first read port couples to the first array and the second array and reads from the first array and the second array. A second read port couples to the first array and reads from the first array. A second write port couples to the second read port, reads from the second read port and writes to the second array.
摘要翻译： 具有依赖矩阵的处理器包括包括多个第一单元的第一阵列。 第二阵列耦合到第一阵列并且包括多个第二单元。 第一个写入端口耦合到第一个阵列和第二个阵列，并写入第一个阵列和第二个阵列。 第一读端口耦合到第一阵列和第二阵列，并从第一阵列和第二阵列读取。 第二个读取端口耦合到第一个数组并从第一个数组读取。 第二个写入端口耦合到第二个读取端口，从第二个读取端口读取并写入第二个数据。
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4.发明授权Apparatus and method for speeding up access time of a large register file with wrap capability 有权用于加速具有包装能力的大型寄存器文件的访问时间的装置和方法公开(公告)号：US07243209B2
公开(公告)日：2007-07-10
申请号：US11044449
申请日：2005-01-27
CPC分类号： G06F9/30141 , G06F9/30098
摘要： An apparatus and method for speeding up access time of a large register file with wrap capability are provided. With the apparatus and method, the 2:1 multiplexers in conventional register file systems are eliminated from the circuit configuration and instead, additional primary multiplexers are provided for half of the addresses, e.g., the first four sub-arrays of the register file for which the wrap capability is needed. These additional primary multiplexers receive the read address and a shifted read word line signal. The other primary multiplexer receives the read address and an unshifted read word line signal. The outputs from the shifted and non-shifted primary multiplexers are provided to a set of secondary multiplexers which multiplex bits from the outputs of the shifted and non-shifted primary multiplexers to generate the read addresses to be used by the multiple read/write register file system.
摘要翻译： 提供了一种用于加速具有包装能力的大型寄存器文件的访问时间的装置和方法。 利用该装置和方法，从电路配置中消除了传统寄存器文件系统中的2：1多路复用器，而是提供了一半地址的附加主复用器，例如寄存器堆的前四个子阵列， 需要包装能力。 这些附加的主多路复用器接收读地址和移位的读字线信号。 另一个主复用器接收读地址和未移位的读字线信号。 来自移位和未移位的主复用器的输出被提供给一组次级多路复用器，它们将来自移位和未移位的主复用器的输出的比特复用以产生要由多个读/写寄存器堆使用的读地址 系统。
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5.发明授权Apparatus and method for providing multiple reads/writes using a 2Read/2Write register file array 有权使用2Read / 2Write寄存器文件阵列提供多次读/写的装置和方法公开(公告)号：US07663963B2
公开(公告)日：2010-02-16
申请号：US12134537
申请日：2008-06-06
IPC分类号： G11C8/00
CPC分类号： G06F9/30141
摘要： An apparatus and method are provided for reading a plurality of consecutive entries and writing a plurality of consecutive entries with only one read address and one write address using a 2Read/2Write register file. In one exemplary embodiment, a 64 entry register file array is partitioned into four sub-arrays. Each sub-array contains sixteen entries having one or more 2Read/2Write SRAM cells. The apparatus and method provide a mechanism to write the consecutive entries by only having a 4 to 16 decode of one address. In addition, the apparatus and method provide a mechanism for reading data from the register file array using a starting read word address and two read word lines generated based on the starting read word address. The two read word lines are used to access the two read ports of the entries in the sub-arrays.
摘要翻译： 提供一种用于读取多个连续条目并使用2Read / 2Write寄存器文件仅写入一个读取地址和一个写入地址的多个连续条目的装置和方法。 在一个示例性实施例中，64个入口寄存器文件阵列被划分为四个子阵列。 每个子阵列包含16个具有一个或多个2Read / 2Write SRAM单元的条目。 该装置和方法提供了通过仅对一个地址进行4到16个解码来写入连续条目的机制。 此外，该装置和方法提供了一种用于使用起始读字地址和基于起始读字地址生成的两个读字线从寄存器堆数组读取数据的机制。 两条读字线用于访问子阵列中条目的两个读端口。
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6.发明授权Method for providing multiple reads/writes using a 2read/2write register file array 有权使用2read / 2write寄存器文件阵列提供多次读/写的方法公开(公告)号：US07400548B2
公开(公告)日：2008-07-15
申请号：US11054276
申请日：2005-02-09
IPC分类号： G11C8/00
CPC分类号： G06F9/30141
摘要： Reading a plurality of consecutive entries and writing a plurality of consecutive entries with only one read address and one write address using a 2Read/2Write register file is provided. In one exemplary embodiment, a 64 entry register file array is partitioned into four sub-arrays. Each sub-array contains sixteen entries having one or more 2Read/2Write SRAM cells. A mechanism to write the consecutive entries by only having a 4 to 16 decode of one address is also provided. In addition, a mechanism for reading data from the register file array using a starting read word address and two read word lines generated based on the starting read word address is provided. The two read word lines are used to access the two read ports of the entries in the sub-arrays.
摘要翻译： 提供了使用2Read / 2Write寄存器文件读取多个连续条目并且仅写入一个读取地址和一个写入地址的多个连续条目。 在一个示例性实施例中，64个入口寄存器文件阵列被划分为四个子阵列。 每个子阵列包含16个具有一个或多个2Read / 2Write SRAM单元的条目。 还提供了通过仅对一个地址进行4至16个解码来写入连续条目的机制。 此外，提供了一种用于使用起始读取字地址和基于起始读取字地址生成的两个读取字线从寄存器堆栈数据读取数据的机制。 两条读字线用于访问子阵列中条目的两个读端口。
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7.发明申请Apparatus and method for providing multiple reads/writes using a 2read/2write register file array 有权使用2read / 2write寄存器文件阵列提供多次读/写的装置和方法公开(公告)号：US20060179257A1
公开(公告)日：2006-08-10
申请号：US11054276
申请日：2005-02-09
申请人： Sam Chu , Maureen Delaney , Saiful Islam , Dung Nguyen , Jafar Nahidi
发明人： Sam Chu , Maureen Delaney , Saiful Islam , Dung Nguyen , Jafar Nahidi
IPC分类号： G06F12/00
CPC分类号： G06F9/30141
摘要： An apparatus and method are provided for reading a plurality of consecutive entries and writing a plurality of consecutive entries with only one read address and one write address using a 2Read/2Write register file. In one exemplary embodiment, a 64 entry register file array is partitioned into four sub-arrays. Each sub-array contains sixteen entries having one or more 2Read/2Write SRAM cells. The apparatus and method provide a mechanism to write the consecutive entries by only having a 4 to 16 decode of one address. In addition, the apparatus and method provide a mechanism for reading data from the register file array using a starting read word address and two read word lines generated based on the starting read word address. The two read word lines are used to access the two read ports of the entries in the sub-arrays.
摘要翻译： 提供一种用于读取多个连续条目并使用2Read / 2Write寄存器文件仅写入一个读取地址和一个写入地址的多个连续条目的装置和方法。 在一个示例性实施例中，64个入口寄存器文件阵列被划分为四个子阵列。 每个子阵列包含16个具有一个或多个2Read / 2Write SRAM单元的条目。 该装置和方法提供了通过仅对一个地址进行4到16个解码来写入连续条目的机制。 此外，该装置和方法提供了一种用于使用起始读字地址和基于起始读字地址生成的两个读字线从寄存器堆数组读取数据的机制。 两条读字线用于访问子阵列中条目的两个读端口。
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8.发明申请Apparatus and method for speeding up access time of a large register file with wrap capability 有权用于加速具有包装能力的大型寄存器文件的访问时间的装置和方法公开(公告)号：US20060171208A1
公开(公告)日：2006-08-03
申请号：US11044449
申请日：2005-01-27
申请人： Sam Chu , Maureen Delaney , Saiful Islam , Jafar Nahidi , Dung Nguyen
发明人： Sam Chu , Maureen Delaney , Saiful Islam , Jafar Nahidi , Dung Nguyen
IPC分类号： G11C7/10
CPC分类号： G06F9/30141 , G06F9/30098
摘要： An apparatus and method for speeding up access time of a large register file with wrap capability are provided. With the apparatus and method, the 2:1 multiplexers in conventional register file systems are eliminated from the circuit configuration and instead, additional primary multiplexers are provided for half of the addresses, e.g., the first four sub-arrays of the register file for which the wrap capability is needed. These additional primary multiplexers receive the read address and a shifted read word line signal. The other primary multiplexer receives the read address and an unshifted read word line signal. The outputs from the shifted and non-shifted primary multiplexers are provided to a set of secondary multiplexers which multiplex bits from the outputs of the shifted and non-shifted primary multiplexers to generate the read addresses to be used by the multiple read/write register file system.
摘要翻译： 提供了一种用于加速具有包装能力的大型寄存器文件的访问时间的装置和方法。 利用该装置和方法，从电路配置中消除了常规寄存器文件系统中的2：1多路复用器，而是提供了一半地址的附加主复用器，例如寄存器堆的前四个子阵列， 需要包装能力。 这些附加的主多路复用器接收读地址和移位的读字线信号。 另一个主复用器接收读地址和未移位的读字线信号。 来自移位和未移位的主复用器的输出被提供给一组次级多路复用器，它们将来自移位和未移位的主复用器的输出的比特复用以产生要由多个读/写寄存器堆使用的读地址 系统。
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公开(公告)号：US20050114603A1
公开(公告)日：2005-05-26
申请号：US10707149
申请日：2003-11-24
申请人： Taqi Buti , Brian Curran , Maureen Delaney , Saiful Islam , Zakaria Khwaja , Jafar Nahidi , Dung Nguyen
发明人： Taqi Buti , Brian Curran , Maureen Delaney , Saiful Islam , Zakaria Khwaja , Jafar Nahidi , Dung Nguyen
CPC分类号： G06F9/3802 , G06F9/3814
摘要： An instruction buffer and a method of buffering instructions. The instruction buffer including: a memory array partitioned into multiple identical memory sub-arrays arranged in sequential order from a first memory sub-array to a last memory sub-array, each memory sub-array having multiple instruction entry positions and adapted to store a different instruction of a set of concurrent instructions in a single instruction entry position of any one of the memory sub-arrays, the set of concurrent instructions arranged in sequential order from a first instruction to a last instruction
摘要翻译： 指令缓冲器和缓冲指令的方法。 所述指令缓冲器包括：分割成从第一存储器子阵列到最后存储器子阵列的顺序排列的多个相同的存储器子阵列的存储器阵列，每个存储器子阵列具有多个指令条目位置，并且适于存储 任何一个存储器子阵列的单个指令输入位置中的一组并行指令的不同指令，以从第一指令到最后指令的顺序排列的并发指令集
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10.发明申请Apparatus and Method for Providing Multiple Reads/Writes Using a 2Read/2Write Register File Array 有权使用2Read / 2Write寄存器文件阵列提供多个读/写的装置和方法公开(公告)号：US20080239860A1
公开(公告)日：2008-10-02
申请号：US12134537
申请日：2008-06-06
IPC分类号： G11C8/00
CPC分类号： G06F9/30141
摘要： An apparatus and method are provided for reading a plurality of consecutive entries and writing a plurality of consecutive entries with only one read address and one write address using a 2Read/2Write register file. In one exemplary embodiment, a 64 entry register file array is partitioned into four sub-arrays. Each sub-array contains sixteen entries having one or more 2Read/2Write SRAM cells. The apparatus and method provide a mechanism to write the consecutive entries by only having a 4 to 16 decode of one address. In addition, the apparatus and method provide a mechanism for reading data from the register file array using a starting read word address and two read word lines generated based on the starting read word address. The two read word lines are used to access the two read ports of the entries in the sub-arrays.
摘要翻译： 提供一种用于读取多个连续条目并使用2Read / 2Write寄存器文件仅写入一个读取地址和一个写入地址的多个连续条目的装置和方法。 在一个示例性实施例中，64个入口寄存器文件阵列被划分为四个子阵列。 每个子阵列包含16个具有一个或多个2Read / 2Write SRAM单元的条目。 该装置和方法提供了通过仅对一个地址进行4到16个解码来写入连续条目的机制。 此外，该装置和方法提供了一种用于使用起始读字地址和基于起始读字地址生成的两个读字线从寄存器堆数组读取数据的机制。 两条读字线用于访问子阵列中条目的两个读端口。
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