公开(公告)号：US07243170B2

公开(公告)日：2007-07-10

申请号：US10707149

申请日：2003-11-24

申请人： Taqi N. Buti ,  Brian W. Curran ,  Maureen A. Delaney ,  Saiful Islam ,  Zakaria M. Khwaja ,  Jafar Nahidi ,  Dung Q. Nguyen

发明人： Taqi N. Buti ,  Brian W. Curran ,  Maureen A. Delaney ,  Saiful Islam ,  Zakaria M. Khwaja ,  Jafar Nahidi ,  Dung Q. Nguyen

IPC分类号： G06F3/00 ,  G06F5/00

CPC分类号： G06F9/3802 ,  G06F9/3814

摘要： An instruction buffer and a method of buffering instructions. The instruction buffer including: a memory array partitioned into multiple identical memory sub-arrays arranged in sequential order from a first memory sub-array to a last memory sub-array, each memory sub-array having multiple instruction entry positions and adapted to store a different instruction of a set of concurrent instructions in a single instruction entry position of any one of the memory sub-arrays, the set of concurrent instructions arranged in sequential order from a first instruction to a last instruction

摘要翻译： 指令缓冲器和缓冲指令的方法。 所述指令缓冲器包括：分割成从第一存储器子阵列到最后存储器子阵列的顺序排列的多个相同的存储器子阵列的存储器阵列，每个存储器子阵列具有多个指令条目位置，并且适于存储 任何一个存储器子阵列的单个指令输入位置中的一组并行指令的不同指令，以从第一指令到最后指令的顺序排列的并发指令集

公开(公告)号：US08725993B2

公开(公告)日：2014-05-13

申请号：US13032737

申请日：2011-02-23

申请人： Christopher M. Abernathy ,  Mary D. Brown ,  Susan E. Eisen ,  James A. Kahle ,  Hung Q. Le ,  Dung Q. Nguyen

发明人： Christopher M. Abernathy ,  Mary D. Brown ,  Susan E. Eisen ,  James A. Kahle ,  Hung Q. Le ,  Dung Q. Nguyen

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

CPC分类号： G06F9/30101 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/461

摘要： Various systems, processes, products, and techniques may be used to manage thread transitions. In particular implementations, a system and process for managing thread transitions may include the ability to determine that a transition is to be made regarding the relative use of two data register sets and determine, based on the transition determination, whether to move thread data in at least one of the data register sets to second-level registers. The system and process may also include the ability to move the thread data from at least one data register set to second-level registers based on the move determination.

摘要翻译： 可以使用各种系统，过程，产品和技术来管理线程转换。 在特定实现中，用于管理线程转换的系统和过程可以包括确定要对两个数据寄存器组的相对使用进行转换的能力，并且基于转换确定来确定是否将线程数据移入 至少一个数据寄存器设置为二级寄存器。 系统和过程还可以包括基于移动确定将线程数据从至少一个数据寄存器集合移动到第二级寄存器的能力。

公开(公告)号：US08037366B2

公开(公告)日：2011-10-11

申请号：US12409981

申请日：2009-03-24

申请人： Christopher M. Abernathy ,  Mary D. Brown ,  Dung Q. Nguyen ,  Todd A. Venton

发明人： Christopher M. Abernathy ,  Mary D. Brown ,  Dung Q. Nguyen ,  Todd A. Venton

IPC分类号： G06F11/00

CPC分类号： G06F11/0793 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/3863 ,  G06F9/3885 ,  G06F11/0721

摘要： A mechanism is provided for issuing instructions. An instruction dispatch unit receives an instruction for dispatch to one of a plurality of execution units. The instruction dispatch unit analyzes a tag register to determine whether a previous tag associated with a previous instruction has been stored in the tag register. Responsive to the previous tag associated with the previous instruction failing to be stored in the tag register, the instruction dispatch unit storing a tag corresponding to the instruction in the tag register. The instruction dispatch unit dispatches the instruction to an issue queue for issue to the one of the plurality of execution units.

摘要翻译： 提供了发出指令的机制。 指令调度单元接收用于发送到多个执行单元之一的指令。 指令调度单元分析标签寄存器以确定与先前指令相关联的先前标签是否已经存储在标签寄存器中。 指令调度单元响应于与先前指令相关联的先前的标签不能存储在标签寄存器中，存储与标签寄存器中的指令相对应的标签。 指令调度单元将指令发送到多个执行单元中的一个执行单元。

公开(公告)号：US20100262807A1

公开(公告)日：2010-10-14

申请号：US12423495

申请日：2009-04-14

申请人： William E. Burky ,  Brian R. Mestan ,  Dung Q. Nguyen ,  Balaram Sinharoy ,  Benjamin W. Stolt

发明人： William E. Burky ,  Brian R. Mestan ,  Dung Q. Nguyen ,  Balaram Sinharoy ,  Benjamin W. Stolt

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3861 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3857

摘要： Mechanisms are provided for partial flush handling with multiple branches per instruction group. The instruction fetch unit sorts instructions into groups. A group may include a floating branch instruction and a boundary branch instruction. For each group of instructions, the instruction sequencing unit creates an entry in a global completion table (GCT), which may also be referred to herein as a group completion table. The instruction sequencing unit uses the GCT to manage completion of instructions within each outstanding group. Because each group may include up to two branches, the instruction sequencing unit may dispatch instructions beyond the first branch, i.e. the floating branch. Therefore, if the floating branch results in a misprediction, the processor performs a partial flush of that group, as well as a flush of every group younger than that group.

摘要翻译： 提供了用于部分刷新处理的机制，每个指令组具有多个分支。 指令提取单元将指令分组分组。 组可以包括浮动分支指令和边界分支指令。 对于每组指令，指令排序单元在全局完成表（GCT）中创建条目，其也可以在此被称为组完成表。 指令排序单元使用GCT来管理每个优秀组内的指令完成。 因为每个组可以包括多达两个分支，所以指令排序单元可以分派指令超出第一分支，即浮动分支。 因此，如果浮动分支导致错误预测，则处理器将对该组进行部分刷新，以及每个小于该组的组的刷新。

公开(公告)号：US20080263331A1

公开(公告)日：2008-10-23

申请号：US11736855

申请日：2007-04-18

申请人： Hung Q. Le ,  Dung Q. Nguyen ,  Balaram Sinharoy

发明人： Hung Q. Le ,  Dung Q. Nguyen ,  Balaram Sinharoy

IPC分类号： G06F9/30

CPC分类号： G06F9/3861 ,  G06F9/384

摘要： A universal register rename mechanism for instructions with multiple targets using a common destination tag. For each instruction that updates multiple destinations, a single rename entry is allocated to handle all destinations associated with it. A rename entry now consists of a DTAG and a vector to indicate the type of destination(s) that is/are being updated by such a particular instruction. For example, a common DTAG can be assigned to a fixed point unit instruction (FXU) that updates general purpose register (GPR), fixed point exception register (XER), and condition code register (CR) destinations. During flush time, the DTAGs in the recovery link may be used to restore the information indicating that the youngest instruction updates a particular architected register. By using a single, universal rename structure for all types of destinations, a large saving in silicon and power can be realized without the need to sacrifice performance.

摘要翻译： 通用寄存器重命名机制，用于使用公共目标标签的多个目标的指令。 对于更新多个目的地的每个指令，分配单个重命名条目来处理与其相关联的所有目的地。 现在，一个重命名条目由一个DTAG和一个向量组成，用于指示由这样的特定指令更新的目标的类型。 例如，可以将普通DTAG分配给更新通用寄存器（GPR），定点异常寄存器（XER）和条件码寄存器（CR）目的地的固定点单元指令（FXU）。 在冲洗时间期间，恢复链路中的DTAG可以用于恢复指示最年轻的指令更新特定架构的寄存器的信息。 通过为所有类型的目的地使用单一的通用重命名结构，可以实现大量的硅和电源节省，而不需要牺牲性能。

公开(公告)号：US20080263321A1

公开(公告)日：2008-10-23

申请号：US11736844

申请日：2007-04-18

申请人： Hung Q. Le ,  Dung Q. Nguyen ,  Balaram Sinharoy

发明人： Hung Q. Le ,  Dung Q. Nguyen ,  Balaram Sinharoy

IPC分类号： G06F15/00

CPC分类号： G06F9/384 ,  G06F9/3838 ,  G06F9/3857 ,  G06F9/3861

摘要： A unified register rename mechanism for targets of different instruction types is provided in a microprocessor. The universal rename mechanism renames destinations of different instruction types using a single rename structure. Thus, an instruction that is updating a floating point register (FPR) can be renamed along with an instruction that is updating a general purpose register (GPR) or vector multimedia extensions (VMX) instructions register (VR) using the same rename structure because the number of architected states for GPR is the same as the number of architected states for FPR and VR. Each destination tag (DTAG) is assigned to one destination. A floating point instruction may be assigned to a DTAG, and then a fixed point instruction may be assigned to the next DTAG and so forth. With a universal rename mechanism, significant silicon and power can be saved by having only one rename structure for all instruction types.

摘要翻译： 在微处理器中提供了用于不同指令类型的目标的统一寄存器重命名机制。 通用重命名机制使用单个重命名结构重命名不同指令​​类型的目标。 因此，更新浮点寄存器（FPR）的指令可以与使用相同的重命名结构更新通用寄存器（GPR）或向量多媒体扩展（VMX）指令寄存器（VR））的指令一起重命名，因为 GPR的架构状态数量与FPR和VR的架构状态数量相同。 每个目的地标签（DTAG）被分配到一个目的地。 可将浮点指令分配给DTAG，然后将固定点指令分配给下一个DTAG等等。 使用通用重命名机制，可以通过为所有指令类型只有一个重命名结构来节省显着的硅和功率。

公开(公告)号：US20080195850A1

公开(公告)日：2008-08-14

申请号：US11674754

申请日：2007-02-14

申请人： Christopher M. Abernathy ,  Mary D. Brown ,  Dung Q. Nguyen ,  Joel A. Silberman

发明人： Christopher M. Abernathy ,  Mary D. Brown ,  Dung Q. Nguyen ,  Joel A. Silberman

IPC分类号： G06F9/38

CPC分类号： G06F9/3863 ,  G06F9/3802 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3885

摘要： A method of restoring register mapper states for an out-of-order microprocessor. A processor maps a logical register to a physical register in a map table in response to a first instruction. Instruction sequencing logic records a second speculatively executed instruction as a most recently dispatched instruction in the map table when the second instruction maps the same logical register of the first instruction. The instruction sequencing logic sets an evictor instruction tag (ITAG) of the first instruction in the map table when the second instruction maps a same logical register of the first instruction. The instruction sequencing logic detects mispredicted speculative instructions, determines which instructions in the map table were dispatched prior to the mispredicted speculative instructions, and restores the map table to a state prior to the mispredicted speculative instructions by utilizing the evictor ITAG to restore one or more A bits in the map table data structure.

摘要翻译： 一种恢复无序微处理器的寄存器映射器状态的方法。 处理器响应于第一指令将逻辑寄存器映射到地图表中的物理寄存器。 当第二指令映射第一指令的相同逻辑寄存器时，指令排序逻辑将第二推测执行指令记录为映射表中最近调度的指令。 当第二指令映射第一指令的相同逻辑寄存器时，指令排序逻辑设置映射表中的第一指令的撤销指令标签（ITAG）。 指令排序逻辑检测误预测的推测指令，确定映射表中的哪些指令在误预测的推测指令之前被分派，并且通过利用驱逐者ITAG恢复一个或多个A，将映射表恢复到误预测的推测指令之前的状态 位图中的数据结构。

公开(公告)号：US20080072018A1

公开(公告)日：2008-03-20

申请号：US11533379

申请日：2006-09-20

申请人： Hung Q. Le ,  Dung Q. Nguyen

发明人： Hung Q. Le ,  Dung Q. Nguyen

IPC分类号： G06F9/30

CPC分类号： G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855

摘要： A method of data processing includes fetching a sequence of instructions, assigning each instruction within the sequence a respective unique instruction tag, and associating a respective destination vector with each instruction. The destination vectors, which are of uniform size, identify which of a plurality of possible destinations for execution results are targeted by the associated instructions. Data dependency between instructions in the sequence is managed by reference to the destination vectors associated with the instructions.

摘要翻译： 一种数据处理方法包括获取一系列指令，在序列内分配相应唯一指令标签中的每条指令，并将各目标向量与每条指令相关联。 具有相同大小的目的地向量识别用于执行结果的多个可能目的地中的哪一个被相关联的指令所针对。 通过参考与指令相关联的目的地向量来管理序列中的指令之间的数据相关性。

公开(公告)号：US08661228B2

公开(公告)日：2014-02-25

申请号：US13448024

申请日：2012-04-16

申请人： Christopher M. Abernathy ,  Mary D. Brown ,  Hung Q. Le ,  Dung Q. Nguyen

发明人： Christopher M. Abernathy ,  Mary D. Brown ,  Hung Q. Le ,  Dung Q. Nguyen

IPC分类号： G06F9/34

CPC分类号： G06F9/3851 ,  G06F9/30138

摘要： A processor includes an instruction fetch unit, an issue queue coupled to the instruction fetch unit, an execution unit coupled to the issue queue, and a multi-level register file including a first level register file having lower access latency and a second level register file having higher access latency. Each of the first and second level register files includes a plurality of physical registers for holding operands that is concurrently shared by a plurality of threads. The processor further includes a mapper that, at dispatch of an instruction specifying a source logical register from the instruction fetch unit to the issue queue, initiates a swap of a first operand associated with the source logical register that is in the second level register file with a second operand held in the first level register file. The issue queue, following the swap, issues the instruction to the execution unit for execution.

公开(公告)号：US07827389B2

公开(公告)日：2010-11-02

申请号：US11763736

申请日：2007-06-15

申请人： Hung Q. Le ,  Dung Q. Nguyen

发明人： Hung Q. Le ,  Dung Q. Nguyen

IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F3/00 ,  G06F5/00

CPC分类号： G06F9/3885 ,  G06F9/30105 ,  G06F9/30116 ,  G06F9/3012 ,  G06F9/30141 ,  G06F9/30181 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3851

摘要： A method, system, and computer program product are provided for enhancing the execution of independent loads in a processing unit. The processing unit dispatches a first set of instructions in order from a first buffer for execution. The processing unit receives updated results from the execution of the first set of instructions. The processing unit updates, in a first register, at least one register entry associated with each instruction in the first set of instructions, with the updated results. The processing unit determines if the first set of instructions from the first buffer have completed execution. Responsive to the completed execution of the first set of instructions from the first buffer, the processing unit copies the set of entries from the first register to a second register.

摘要翻译： 提供了一种方法，系统和计算机程序产品，用于增强处理单元中独立负载的执行。 处理单元从第一缓冲器依次调度第一组指令以执行。 处理单元从执行第一组指令接收更新的结果。 处理单元在第一寄存器中更新与第一组指令中的每个指令相关联的至少一个寄存器条目以及更新的结果。 处理单元确定来自第一缓冲器的第一组指令是否已经完成执行。 响应于来自第一缓冲器的第一组指令的完成执行，处理单元将该组条目从第一寄存器复制到第二寄存器。