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    Back-end-of-line resistive semiconductor structures
    21.
    发明授权
    Back-end-of-line resistive semiconductor structures 有权
    后端电阻半导体结构

    公开(公告)号：US07939911B2

    公开(公告)日：2011-05-10

    申请号：US12191683

    申请日：2008-08-14

    申请人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Jed H. Rankin ,  Robert Robison ,  Yun Shi ,  William R. Tonti

    发明人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Jed H. Rankin ,  Robert Robison ,  Yun Shi ,  William R. Tonti

    IPC分类号： H01L29/00

    CPC分类号： H01L27/115 ,  H01L23/5256 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In one embodiment, a back-end-of-line (BEOL) resistive structure comprises a second metal line embedded in a second dielectric layer and overlying a first metal line embedded in a first dielectric layer. A doped semiconductor spacer or plug laterally abutting sidewalls of the second metal line and vertically abutting a top surface of the first metal line provides a resistive link between the first and second metal lines. In another embodiment, another BEOL resistive structure comprises a first metal line and a second metal line are embedded in a dielectric layer. A doped semiconductor spacer or plug laterally abutting the sidewalls of the first and second metal lines provides a resistive link between the first and second metal lines.

    摘要翻译： 在一个实施例中，后端行（BEOL）电阻结构包括嵌入在第二电介质层中的第二金属线，并且覆盖嵌入在第一介电层中的第一金属线。 横向邻接第二金属线的侧壁并垂直邻接第一金属线的顶表面的掺杂半导体间隔物或插塞提供第一和第二金属线之间的电阻连接。 在另一个实施例中，另一个BEOL电阻结构包括第一金属线，第二金属线嵌入电介质层。 横向邻接第一和第二金属线的侧壁的掺杂半导体间隔件或插塞提供第一和第二金属线之间的电阻连接。

    Device structures for a metal-oxide-semiconductor field effect transistor and methods of fabricating such device structures
    23.
    发明授权
    Device structures for a metal-oxide-semiconductor field effect transistor and methods of fabricating such device structures 失效
    金属氧化物半导体场效应晶体管的器件结构及其制造方法

    公开(公告)号：US07790543B2

    公开(公告)日：2010-09-07

    申请号：US11972941

    申请日：2008-01-11

    申请人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Jed H. Rankin ,  Yun Shi ,  William R. Tonti

    发明人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Jed H. Rankin ,  Yun Shi ,  William R. Tonti

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795

    摘要： Device structures for a metal-oxide-semiconductor field effect transistor (MOSFET) that is suitable for operation at relatively high voltages and methods of forming same. The MOSFET, which is formed using a semiconductor-on-insulator (SOI) substrate, includes a channel in a semiconductor body that is self-aligned with a gate electrode. The gate electrode and semiconductor body, which are both formed from the monocrystalline SOI layer of the SOI substrate, are separated by a gap that is filled by a gate dielectric layer. The gate dielectric layer may be composed of thermal oxide layers grown on adjacent sidewalls of the semiconductor body and gate electrode, in combination with an optional deposited dielectric material that fills the remaining gap between the thermal oxide layers.

    摘要翻译： 适用于在较高电压下工作的金属氧化物半导体场效应晶体管（MOSFET）的器件结构及其形成方法。 使用绝缘体上半导体（SOI）衬底形成的MOSFET包括半导体本体中与栅电极自对准的沟道。 由SOI衬底的单晶SOI层形成的栅电极和半导体本体由被栅极电介质层填充的间隙分开。 栅极电介质层可以由在半导体主体和栅电极的相邻侧壁上生长的热氧化物层组合，并与填充热氧化物层之间的剩余间隙的任选沉积的电介质材料组合。

    Device and design structures for memory cells in a non-volatile random access memory and methods of fabricating such device structures
    24.
    发明授权
    Device and design structures for memory cells in a non-volatile random access memory and methods of fabricating such device structures 失效
    用于非易失性随机存取存储器中的存储器单元的装置和设计结构以及制造这种器件结构的方法

    公开(公告)号：US07790524B2

    公开(公告)日：2010-09-07

    申请号：US11972949

    申请日：2008-01-11

    申请人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Jed H. Rankin ,  Yun Shi ,  William R. Tonti

    发明人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Jed H. Rankin ,  Yun Shi ,  William R. Tonti

    IPC分类号： H01L21/00

    CPC分类号： H01L29/7881 ,  H01L29/66825

    摘要： Device and design structures for memory cells in a non-volatile random access memory (NVRAM) and methods for fabricating such device structures using complementary metal-oxide-semiconductor (CMOS) processes. The device structure, which is formed using a semiconductor-on-insulator (SOI) substrate, includes a floating gate electrode, a semiconductor body, and a control gate electrode separated from the semiconductor body by the floating gate electrode. The floating gate electrode, the control gate electrode, and the semiconductor body, which are both formed from the monocrystalline SOI layer of the SOI substrate, are respectively separated by dielectric layers. The dielectric layers may each be composed of thermal oxide layers grown on confronting sidewalls of the semiconductor body, the floating gate electrode, and the control gate electrode. An optional deposited dielectric material may fill any remaining gap between either pair of the thermal oxide layers.

    摘要翻译： 用于非易失性随机存取存储器（NVRAM）中的存储器单元的装置和设计结构以及使用互补金属氧化物半导体（CMOS）工艺制造这种器件结构的方法。 使用绝缘体上半导体（SOI）衬底形成的器件结构包括通过浮栅电极与半导体本体分离的浮栅电极，半导体本体和控制栅电极。 由SOI衬底的单晶SOI层形成的浮置栅电极，控制栅电极和半导体本体分别由电介质层分离。 介电层可以各自由在半导体本体，浮栅电极和控制栅电极的相对侧壁上生长的热氧化物层组成。 任选沉积的介电材料可以填充任何一对热氧化物层之间的剩余间隙。

    DEVICE STRUCTURES FOR A METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTOR AND METHODS OF FABRICATING SUCH DEVICE STRUCTURES
    25.
    发明申请
    DEVICE STRUCTURES FOR A METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTOR AND METHODS OF FABRICATING SUCH DEVICE STRUCTURES 失效
    金属氧化物半导体场效应晶体管的器件结构和制造这种器件结构的方法

    公开(公告)号：US20090179266A1

    公开(公告)日：2009-07-16

    申请号：US11972941

    申请日：2008-01-11

    申请人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  Yun Shi ,  William R. Tonti

    发明人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  Yun Shi ,  William R. Tonti

    IPC分类号： H01L27/12 ,  H01L21/782

    CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795

    摘要： Device structures for a metal-oxide-semiconductor field effect transistor (MOSFET) that is suitable for operation at relatively high voltages and methods of forming same. The MOSFET, which is formed using a semiconductor-on-insulator (SOI) substrate, includes a channel in a semiconductor body that is self-aligned with a gate electrode. The gate electrode and semiconductor body, which are both formed from the monocrystalline SOI layer of the SOI substrate, are separated by a gap that is filled by a gate dielectric layer. The gate dielectric layer may be composed of thermal oxide layers grown on adjacent sidewalls of the semiconductor body and gate electrode, in combination with an optional deposited dielectric material that fills the remaining gap between the thermal oxide layers.

    摘要翻译： 适用于在较高电压下工作的金属氧化物半导体场效应晶体管（MOSFET）的器件结构及其形成方法。 使用绝缘体上半导体（SOI）衬底形成的MOSFET包括半导体本体中与栅电极自对准的沟道。 由SOI衬底的单晶SOI层形成的栅电极和半导体本体由被栅极电介质层填充的间隙分开。 栅极电介质层可以由在半导体主体和栅电极的相邻侧壁上生长的热氧化物层组合，并与填充热氧化物层之间的剩余间隙的任选沉积的电介质材料组合。

    DEVICE AND DESIGN STRUCTURES FOR MEMORY CELLS IN A NON-VOLATILE RANDOM ACCESS MEMORY AND METHODS OF FABRICATING SUCH DEVICE STRUCTURES
    26.
    发明申请
    DEVICE AND DESIGN STRUCTURES FOR MEMORY CELLS IN A NON-VOLATILE RANDOM ACCESS MEMORY AND METHODS OF FABRICATING SUCH DEVICE STRUCTURES 失效
    非易失性随机存取存储器中的存储器单元的设备和设计结构以及制造这种器件结构的方法

    公开(公告)号：US20090179251A1

    公开(公告)日：2009-07-16

    申请号：US11972949

    申请日：2008-01-11

    申请人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  Yun Shi ,  William R. Tonti

    发明人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  Yun Shi ,  William R. Tonti

    IPC分类号： H01L29/786 ,  H01L21/336

    CPC分类号： H01L29/7881 ,  H01L29/66825

    摘要： Device and design structures for memory cells in a non-volatile random access memory (NVRAM) and methods for fabricating such device structures using complementary metal-oxide-semiconductor (CMOS) processes. The device structure, which is formed using a semiconductor-on-insulator (SOI) substrate, includes a floating gate electrode, a semiconductor body, and a control gate electrode separated from the semiconductor body by the floating gate electrode. The floating gate electrode, the control gate electrode, and the semiconductor body, which are both formed from the monocrystalline SOI layer of the SOI substrate, are respectively separated by dielectric layers. The dielectric layers may each be composed of thermal oxide layers grown on confronting sidewalls of the semiconductor body, the floating gate electrode, and the control gate electrode. An optional deposited dielectric material may fill any remaining gap between either pair of the thermal oxide layers.

    摘要翻译： 用于非易失性随机存取存储器（NVRAM）中的存储器单元的装置和设计结构以及使用互补金属氧化物半导体（CMOS）工艺制造这种器件结构的方法。 使用绝缘体上半导体（SOI）衬底形成的器件结构包括通过浮栅电极与半导体本体分离的浮栅电极，半导体本体和控制栅电极。 由SOI衬底的单晶SOI层形成的浮置栅电极，控制栅电极和半导体本体分别由电介质层分离。 介电层可以各自由在半导体本体，浮栅电极和控制栅电极的相对侧壁上生长的热氧化物层组成。 任选沉积的介电材料可以填充任何一对热氧化物层之间的剩余间隙。

    Method and structure to process thick and thin fins and variable fin to fin spacing
    27.
    发明授权
    Method and structure to process thick and thin fins and variable fin to fin spacing 有权
    处理厚薄翅片和可变翅片翅片间距的方法和结构

    公开(公告)号：US07763531B2

    公开(公告)日：2010-07-27

    申请号：US11846544

    申请日：2007-08-29

    申请人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  Kiran V. Chatty ,  Robert J. Gauthler, Jr. ,  Jed H. Rankin ,  William R. Tonti

    发明人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  Kiran V. Chatty ,  Robert J. Gauthler, Jr. ,  Jed H. Rankin ,  William R. Tonti

    IPC分类号： H01L21/425

    CPC分类号： B07C5/344 ,  G01R31/2831

    摘要： The disclosure describes an integrated circuit with multiple semiconductor fins having different widths and variable spacing on the same substrate. The method of forming the circuit incorporates a sidewall image transfer process using different types of mandrels. Fin thickness and fin-to-fin spacing are controlled by an oxidation process used to form oxide sidewalls on the mandrels, and more particularly, by the processing time and the use of intrinsic, oxidation-enhancing and/or oxidation-inhibiting mandrels. Fin thickness is also controlled by using sidewalls spacers combined with or instead of the oxide sidewalls. Specifically, images of the oxide sidewalls alone, images of sidewall spacers alone, and/or combined images of sidewall spacers and oxide sidewalls are transferred into a semiconductor layer to form the fins. The fins with different thicknesses and variable spacing can be used to form a single multiple-fin FETs.

    摘要翻译： 本公开描述了在同一衬底上具有多个半导体鳍片的集成电路，其具有不同的宽度和可变间隔。 形成电路的方法包括使用不同类型的心轴的侧壁图像转印过程。 翅片厚度和翅片翅片间距由用于在心轴上形成氧化物侧壁的氧化工艺控制，更具体地，通过处理时间和使用固有的，氧化增强的和/或氧化抑制的心轴来控制。 翅片厚度也通过使用与氧化物侧壁结合或代替氧化物侧壁的侧壁间隔来控制。 具体地，单独的氧化物侧壁的图像，侧壁间隔物的图像和/或侧壁间隔物和氧化物侧壁的组合图像被转移到半导体层中以形成散热片。 可以使用具有不同厚度和可变间隔的散热片来形成单个多鳍FET。

    MOSFET with decoupled halo before extension
    28.
    发明授权
    MOSFET with decoupled halo before extension 有权
    扩展前分离光环的MOSFET

    公开(公告)号：US06730552B1

    公开(公告)日：2004-05-04

    申请号：US10604096

    申请日：2003-06-26

    申请人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Carl J. Radens ,  William R. Tonti

    发明人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Carl J. Radens ,  William R. Tonti

    IPC分类号： H01L21336

    CPC分类号： H01L29/66492 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/6659 ,  H01L29/7833

    摘要： An inverse-T transistor is formed by a method that decouples the halo implant, the deep S/D implant and the extension implant, so that the threshold voltage can be set by adjusting the halo implant without being affected by changes to the extension implant that are intended to alter the series resistance of the device. Formation of the inverse-T structure can be made by a damascene method in which a temporary layer deposited over the layer that will form the cross bar of the T has an aperture formed in it to hold the gate electrode, the aperture being lined with vertical sidewalls that provide space for the ledges that form the T. Another method of gate electrode formation starts with a layer of poly, forms a block for the gate electrode, covers the horizontal surfaces outside the gate with an etch-resistant material and etches horizontally to remove material above the cross bars on the T, the cross bars being protected by the etch resistant material.

    摘要翻译： 反向T晶体管通过使晕轮注入，深S / D注入和延伸注入分离的方法形成，使得阈值电压可以通过调整晕轮植入来设定，而不受扩展植入物的变化的影响 旨在改变装置的串联电阻。 逆T结构的形成可以通过镶嵌方法来形成，其中沉积在层上的临时层将形成T的横杆，其中形成有形成在其中的孔以保持栅电极，孔径垂直排列 为形成T的壁架提供空间的侧壁。栅电极形成的另一种方法从多层开始，形成用于栅电极的块，用耐蚀刻材料覆盖栅极外的水平表面，并水平蚀刻 去除T上的横杆上方的材料，横杆由耐蚀刻材料保护。

    MOSFET with decoupled halo before extension
    29.
    发明授权
    MOSFET with decoupled halo before extension 失效
    扩展前分离光环的MOSFET

    公开(公告)号：US07253066B2

    公开(公告)日：2007-08-07

    申请号：US10785895

    申请日：2004-02-24

    申请人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Carl J. Radens ,  William R. Tonti

    发明人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Carl J. Radens ,  William R. Tonti

    IPC分类号： H01L21/336

    CPC分类号： H01L29/6653 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/66553 ,  H01L29/6659

    摘要： An inverse-T transistor is formed by a method that decouples the halo implant, the deep S/D implant and the extension implant, so that the threshold voltage can be set by adjusting the halo implant without being affected by changes to the extension implant that are intended to alter the series resistance of the device. Formation of the inverse-T structure can be made by a damascene method in which a temporary layer deposited over the layer that will form the cross bar of the T has an aperture formed in it to hold the gate electrode, the aperture being lined with vertical sidewalls that provide space for the ledges that form the T. Another method of gate electrode formation starts with a layer of poly, forms a block for the gate electrode, covers the horizontal surfaces outside the gate with an etch-resistant material and etches horizontally to remove material above the cross bars on the T, the cross bars being protected by the etch resistant material.

    摘要翻译： 反向T晶体管通过使晕轮注入，深S / D注入和延伸注入分离的方法形成，使得阈值电压可以通过调整晕轮植入来设定，而不受扩展植入物的变化的影响 旨在改变装置的串联电阻。 逆T结构的形成可以通过镶嵌方法来形成，其中沉积在层上的临时层将形成T的横杆，其中形成有形成在其中的孔以保持栅电极，孔径垂直排列 为形成T的壁架提供空间的侧壁。栅电极形成的另一种方法从多层开始，形成用于栅电极的块，用耐蚀刻材料覆盖栅极外的水平表面，并水平蚀刻 去除T上的横杆上方的材料，横杆由耐蚀刻材料保护。