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    Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure
    1.
    发明授权
    Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure 失效
    基于相同测试结构的半导体应力诱发缺陷和反熔丝的测试结构和方法

    公开(公告)号：US06770907B2

    公开(公告)日：2004-08-03

    申请号：US10449426

    申请日：2003-05-30

    申请人： Wagdi W. Abadeer ,  Eric Adler ,  Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Jonathan M. McKenna ,  Jed H. Rankin ,  Edward W. Sengle ,  William R. Tonti

    发明人： Wagdi W. Abadeer ,  Eric Adler ,  Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Jonathan M. McKenna ,  Jed H. Rankin ,  Edward W. Sengle ,  William R. Tonti

    IPC分类号： H01L2358

    CPC分类号： H01L22/34 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for detecting semiconductor process stress-induced defects. The method comprising: providing a polysilicon-bounded test diode, the diode comprising a diffused first region within an upper portion of a second region of a silicon substrate, the second region of an opposite dopant type from the first region, the first region surrounded by a peripheral dielectric isolation, a peripheral polysilicon gate comprising a polysilicon layer over a dielectric layer and the gate overlapping a peripheral portion of the first region; stressing the diode; and monitoring the stressed diode for spikes in gate current during the stress, determining the frequency distribution of the slope of the forward bias voltage versus the first region current at the pre-selected forward bias voltage and monitoring, after stress, the diode for soft breakdown. A DRAM cell may be substituted for the diode. The use of the diode as an antifuse is also disclosed.

    摘要翻译： 一种检测半导体工艺应力诱发缺陷的方法。 该方法包括：提供多晶硅界限的测试二极管，二极管包括在硅衬底的第二区域的上部内的扩散的第一区域，与第一区域相反的掺杂剂类型的第二区域，第一区域由 外围电介质隔离，外围多晶硅栅极，包括介电层上的多晶硅层，栅极与第一区域的周边部分重叠; 强调二极管; 并且在应力期间监视施加二极管的栅极电流尖峰，确定正向偏置电压的斜率与预先选择的正向偏置电压下的第一区域电流的频率分布，并且在应力之后监视用于软击穿的二极管 。 DRAM单元可以代替二极管。 还公开了使用二极管作为反熔丝。

    Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure
    3.
    发明授权
    Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure 失效
    基于相同测试结构的半导体应力诱发缺陷和反熔丝的测试结构和方法

    公开(公告)号：US06624031B2

    公开(公告)日：2003-09-23

    申请号：US09989850

    申请日：2001-11-20

    申请人： Wagdi W. Abadeer ,  Eric Adler ,  Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Jonathan M. McKenna ,  Jed H. Rankin ,  Edward W. Sengle ,  William R. Tonti

    发明人： Wagdi W. Abadeer ,  Eric Adler ,  Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Jonathan M. McKenna ,  Jed H. Rankin ,  Edward W. Sengle ,  William R. Tonti

    IPC分类号： H01L21336

    CPC分类号： H01L22/34 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for detecting semiconductor process stress-induced defects. The method comprising: providing a polysilicon-bounded test diode, the diode comprising a diffused first region within an upper portion of a second region of a silicon substrate, the second region of an opposite dopant type from the first region, the first region surrounded by a peripheral dielectric isolation, a peripheral polysilicon gate comprising a polysilicon layer over a dielectric layer and the gate overlapping a peripheral portion of the first region; stressing the diode; and monitoring the stressed diode for spikes in gate current during the stress, determining the frequency distribution of the slope of the forward bias voltage versus the first region current at the pre-selected forward bias voltage and monitoring, after stress, the diode for soft breakdown. A DRAM cell may,be substituted for the diode. The use of the diode as an antifuse is also disclosed.

    摘要翻译： 一种检测半导体工艺应力诱发缺陷的方法。 该方法包括：提供多晶硅界限的测试二极管，二极管包括在硅衬底的第二区域的上部内的扩散的第一区域，与第一区域相反的掺杂剂类型的第二区域，第一区域由 外围电介质隔离，外围多晶硅栅极，包括介电层上的多晶硅层，栅极与第一区域的周边部分重叠; 强调二极管; 并且在应力期间监视施加二极管的栅极电流尖峰，确定正向偏置电压的斜率与预先选择的正向偏置电压下的第一区域电流的频率分布，并且在应力之后监视用于软击穿的二极管 。 二极管可代替DRAM单元。 还公开了使用二极管作为反熔丝。

    Method of determining dielectric time-to-breakdown
    4.
    发明授权
    Method of determining dielectric time-to-breakdown 失效
    确定介电时间分解的方法

    公开(公告)号：US06188234B1

    公开(公告)日：2001-02-13

    申请号：US09226676

    申请日：1999-01-07

    申请人： Wagdi W. Abadeer ,  Jonathan M. McKenna

    发明人： Wagdi W. Abadeer ,  Jonathan M. McKenna

    IPC分类号： G01R3126

    CPC分类号： G01R31/129 ,  G01R31/2623

    摘要： A method of determining time-to-breakdown of a gate dielectric in an NFET or a PFET transistor. For an NFET transistor, the method includes providing an N+ injector ring in the p-substrate and forward biasing the N+ injector ring with respect to the p-substrate. A first positive reference voltage level is applied to the source and the drain regions. A second positive reference voltage level is applied to the gate dielectric. The first and second positive reference voltage levels are maintained on the transistor until breakdown of the gate dielectric occurs. Another embodiment of the method may be used in a PFET transistor.

    摘要翻译： 一种确定NFET或PFET晶体管中栅极电介质的击穿时间的方法。 对于NFET晶体管，该方法包括在p-衬底中提供N +注入环，并相对于p-衬底向前偏置N +注入环。 第一正参考电压电平施加到源区和漏区。 第二正参考电压电平施加到栅极电介质。 在晶体管上保持第一和第二正参考电压电平，直到栅极电介质发生击穿。 该方法的另一实施例可以用在PFET晶体管中。