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    NON-CONTINUOUS ENCAPSULATION LAYER FOR MIM CAPACITOR
    3.
    发明申请
    NON-CONTINUOUS ENCAPSULATION LAYER FOR MIM CAPACITOR 有权
    MIM电容器的非连续封装层

    公开(公告)号：US20050189615A1

    公开(公告)日：2005-09-01

    申请号：US10908491

    申请日：2005-05-13

    申请人： Wagdi Abadeer ,  Eric Adler ,  Zhong-Xiang He ,  Bradley Orner ,  Vidhya Ramachandran ,  Barbara Waterhouse ,  Michael Zierak

    发明人： Wagdi Abadeer ,  Eric Adler ,  Zhong-Xiang He ,  Bradley Orner ,  Vidhya Ramachandran ,  Barbara Waterhouse ,  Michael Zierak

    IPC分类号： H01L21/02 ,  H01L21/8242

    CPC分类号： H01L28/57

    摘要： The present invention relates to metal-insulator-metal (MIM) capacitors and field effect transistors (FETs) formed on a semiconductor substrate. The FETs are formed in Front End of Line (FEOL) levels below the MIM capacitors which are formed in upper Back End of Line (BEOL) levels. An insulator layer is selectively formed to encapsulate at least a top plate of the MIM capacitor to protect the MIM capacitor from damage due to process steps such as, for example, reactive ion etching. By selective formation of the insulator layer on the MIM capacitor, openings in the inter-level dielectric layers are provided so that hydrogen and/or deuterium diffusion to the FETs can occur.

    摘要翻译： 本发明涉及形成在半导体衬底上的金属 - 绝缘体 - 金属（MIM）电容器和场效应晶体管（FET）。 FET形成在线路前端（FEOL）电平以下的MIM电容器下面，这些电容器形成在上部后端（BEOL）电平。 选择性地形成绝缘体层以封装MIM电容器的至少顶板，以保护MIM电容器免受由于诸如反应离子蚀刻等工艺步骤的损害。 通过在MIM电容器上选择性地形成绝缘体层，提供层间电介质层中的开口，使得可以发生氢和/或氘到FET的扩散。

    Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure
    4.
    发明授权
    Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure 失效
    基于相同测试结构的半导体应力诱发缺陷和反熔丝的测试结构和方法

    公开(公告)号：US06770907B2

    公开(公告)日：2004-08-03

    申请号：US10449426

    申请日：2003-05-30

    申请人： Wagdi W. Abadeer ,  Eric Adler ,  Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Jonathan M. McKenna ,  Jed H. Rankin ,  Edward W. Sengle ,  William R. Tonti

    发明人： Wagdi W. Abadeer ,  Eric Adler ,  Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Jonathan M. McKenna ,  Jed H. Rankin ,  Edward W. Sengle ,  William R. Tonti

    IPC分类号： H01L2358

    CPC分类号： H01L22/34 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for detecting semiconductor process stress-induced defects. The method comprising: providing a polysilicon-bounded test diode, the diode comprising a diffused first region within an upper portion of a second region of a silicon substrate, the second region of an opposite dopant type from the first region, the first region surrounded by a peripheral dielectric isolation, a peripheral polysilicon gate comprising a polysilicon layer over a dielectric layer and the gate overlapping a peripheral portion of the first region; stressing the diode; and monitoring the stressed diode for spikes in gate current during the stress, determining the frequency distribution of the slope of the forward bias voltage versus the first region current at the pre-selected forward bias voltage and monitoring, after stress, the diode for soft breakdown. A DRAM cell may be substituted for the diode. The use of the diode as an antifuse is also disclosed.

    摘要翻译： 一种检测半导体工艺应力诱发缺陷的方法。 该方法包括：提供多晶硅界限的测试二极管，二极管包括在硅衬底的第二区域的上部内的扩散的第一区域，与第一区域相反的掺杂剂类型的第二区域，第一区域由 外围电介质隔离，外围多晶硅栅极，包括介电层上的多晶硅层，栅极与第一区域的周边部分重叠; 强调二极管; 并且在应力期间监视施加二极管的栅极电流尖峰，确定正向偏置电压的斜率与预先选择的正向偏置电压下的第一区域电流的频率分布，并且在应力之后监视用于软击穿的二极管 。 DRAM单元可以代替二极管。 还公开了使用二极管作为反熔丝。

    Method of forming a body contact using BOX modification
    6.
    发明授权
    Method of forming a body contact using BOX modification 失效
    使用BOX修饰形成身体接触的方法

    公开(公告)号：US06531375B1

    公开(公告)日：2003-03-11

    申请号：US09955375

    申请日：2001-09-18

    申请人： Kenneth J. Giewont ,  Eric Adler ,  Neena Garg ,  Michael J. Hargrove ,  Charles W. Koburger, III ,  Junedong Lee ,  Dominic J. Schepis ,  Isabel Ying Yang

    发明人： Kenneth J. Giewont ,  Eric Adler ,  Neena Garg ,  Michael J. Hargrove ,  Charles W. Koburger, III ,  Junedong Lee ,  Dominic J. Schepis ,  Isabel Ying Yang

    IPC分类号： H01L2176

    CPC分类号： H01L21/76264 ,  H01L21/76267

    摘要： A novel method for forming substrate contact regions on a SOI substrate without requiring additional space, and in order to provide lower diffusion capacitance. The method utilizes known semiconductor processing techniques. This method for selectively modifying the BOX region of a SOI substrate involves first providing a silicon substrate. Then, ion implanting the base using SIMOX techniques (e.g. O2 implant) is accomplished. Next, the substrate is photopatterned to protect the modified BOX region. Then, further ion implanting using a “touch-up” O2 implant is accomplished, thereby resulting in a good quality BOX as typically practiced. The final step is annealing the substrate. The area of the substrate, which had a mask present, would not receive the “touch-up” O2 implant (second ion implant), which in turn would result in a leaky BOX.

    摘要翻译： 一种用于在SOI衬底上形成衬底接触区而不需要额外空间的新方法，并且为了提供较低的扩散电容。 该方法利用已知的半导体处理技术。 这种用于选择性地修改SOI衬底的BOX区域的方法包括首先提供硅衬底。 然后，使用SIMOX技术（例如，O 2注入）离子注入基底。 接下来，对基板进行光图案化以保护修改的BOX区域。 然后，使用“接触式”O2注入进一步进行离子注入，从而得到通常实施的良好质量BOX。 最后一步是退火基板。 存在掩模的衬底的区域将不会接收“接触”O 2注入（第二离子注入），这反过来将导致泄漏BOX。

    Sidewall strap
    10.
    发明授权
    Sidewall strap 失效
    侧壁带

    公开(公告)号：US5521118A

    公开(公告)日：1996-05-28

    申请号：US440574

    申请日：1995-05-15

    申请人： Chung H. Lam ,  James S. Nakos ,  Donald M. Kenney ,  Eric Adler

    发明人： Chung H. Lam ,  James S. Nakos ,  Donald M. Kenney ,  Eric Adler

    IPC分类号： H01L21/768 ,  H01L21/8242 ,  H01L23/485 ,  H01L21/283

    CPC分类号： H01L27/10861 ,  H01L21/76897 ,  H01L23/485 ,  H01L2924/0002 ,  Y10S257/90

    摘要： The present invention is a sidewall connector providing a conductive path linking at least two conductive regions. The sidewall connector has a top portion comprising an outer surface. A conductive member contacts the top portion, connecting the rail to a conductive region or to an external conductor. An etch stop layer located on a conductive region can be used to protect the conductive region during the directional etch to form the sidewall connector. A conductive bridge is then used to link exposed portions of the conductive region and the conductive sidewall rail, the conductive bridge extending across the thickness of the etch stop layer. A "T" connector is formed by the process, starting with a pair of intersecting sidewalls wherein the two sidewalls have top edges at different heights where they intersect. The connector is used to form a strap for a DRAM cell.

    摘要翻译： 本发明是提供连接至少两个导电区域的导电路径的侧壁连接器。 侧壁连接器具有包括外表面的顶部部分。 导电构件接触顶部，将轨道连接到导电区域或外部导体。 位于导电区域上的蚀刻停止层可用于在定向蚀刻期间保护导电区域以形成侧壁连接器。 然后使用导电桥连接导电区域和导电侧壁导轨的暴露部分，导电桥延伸跨越蚀刻停止层的厚度。 通过该过程形成“T”连接器，从一对相交的侧壁开始，其中两个侧壁具有与其相交的不同高度的顶部边缘。 连接器用于形成用于DRAM单元的带子。