公开(公告)号：US20060214185A1

公开(公告)日：2006-09-28

申请号：US11422560

申请日：2006-06-06

申请人： Jia Zhen Zheng ,  Weining Li ,  Tze Ho Simon Chan ,  Pradeep Yelehanka

发明人： Jia Zhen Zheng ,  Weining Li ,  Tze Ho Simon Chan ,  Pradeep Yelehanka

IPC分类号： H01L29/74

CPC分类号： H01L27/11 ,  H01L27/0617 ,  H01L29/66393 ,  H01L29/7436

摘要： An integrated circuit structure includes providing a semiconductor substrate and forming a trench therein. A thyristor is formed around the trench and within the semiconductor substrate. The thyristor has at least four layers with three P-N junctions therebetween. A gate for the thyristor is formed within the trench. An access transistor is formed on the semiconductor substrate. An interconnect is formed between the thyristor and the access transistor.

摘要翻译： 集成电路结构包括提供半导体衬底并在其中形成沟槽。 在沟槽周围和半导体衬底内形成晶闸管。 晶闸管具有至少四层，其间具有三个P-N结。 晶闸管的栅极形成在沟槽内。 在半导体衬底上形成存取晶体管。 在晶闸管和存取晶体管之间形成互连。

公开(公告)号：US07081378B2

公开(公告)日：2006-07-25

申请号：US10752357

申请日：2004-01-05

申请人： Jia Zhen Zheng ,  Weining Li ,  Tze Ho Simon Chan ,  Pradeep Ramachandramurthy Yelehanka

发明人： Jia Zhen Zheng ,  Weining Li ,  Tze Ho Simon Chan ,  Pradeep Ramachandramurthy Yelehanka

IPC分类号： H01L21/332

CPC分类号： H01L27/11 ,  H01L27/0617 ,  H01L29/66393 ,  H01L29/7436

摘要： A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming a trench therein. A thyristor is formed around the trench and within the semiconductor substrate. The thyristor has at least four layers with three P-N junctions therebetween. A gate for the thyristor is formed within the trench. An access transistor is formed on the semiconductor substrate. An interconnect is formed between the thyristor and the access transistor.

摘要翻译： 一种用于制造集成电路结构的方法包括提供半导体衬底并在其中形成沟槽。 在沟槽周围和半导体衬底内形成晶闸管。 晶闸管具有至少四层，其间具有三个P-N结。 晶闸管的栅极形成在沟槽内。 在半导体衬底上形成存取晶体管。 在晶闸管和存取晶体管之间形成互连。

公开(公告)号：US07015101B2

公开(公告)日：2006-03-21

申请号：US10683052

申请日：2003-10-09

申请人： Jia Zhen Zheng ,  Pradeep Ramachandramurthy Yelehanka ,  Weining Li

发明人： Jia Zhen Zheng ,  Pradeep Ramachandramurthy Yelehanka ,  Weining Li

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11573

摘要： A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming a gate dielectric layer over the semiconductor substrate. The gate dielectric layer is formed in a plurality of thicknesses in a plurality of devices regions over the semiconductor substrate. A second dielectric layer is formed over at least one of the devices regions. A third dielectric layer is formed over at least a portion of the second dielectric layer. Ion traps are then selectively implanted in portions of the second dielectric layer.

摘要翻译： 一种用于制造集成电路结构的方法包括提供半导体衬底并在半导体衬底上形成栅介质层。 栅极电介质层在半导体衬底上的多个器件区域中形成多个厚度。 在至少一个器件区域上形成第二介电层。 在第二电介质层的至少一部分上形成第三电介质层。 然后在第二介电层的部分中选择性地注入离子阱。

公开(公告)号：US20050167664A1

公开(公告)日：2005-08-04

申请号：US11077731

申请日：2005-03-10

申请人： Elgin Quek ,  Jia Zheng ,  Pradeep Yelehanka ,  Weining Li

发明人： Elgin Quek ,  Jia Zheng ,  Pradeep Yelehanka ,  Weining Li

IPC分类号： H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L29/76

CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0657 ,  H01L29/66378 ,  H01L29/66393 ,  H01L29/66795

摘要： An integrated circuit structure includes a semiconductor substrate and a horizontal semiconductor fin on top of the semiconductor substrate. An access transistor gate and a thyristor gate are on top of the semiconductor substrate and in contact with the horizontal semiconductor fin. An access transistor is at least a portion of the horizontal semiconductor fin and the access transistor gate. A thyristor is at least a portion of the horizontal semiconductor fin and the thyristor gate, the access transistor is in contact with the thyristor.

摘要翻译： 集成电路结构包括在半导体衬底的顶部上的半导体衬底和水平半导体鳍片。 存取晶体管栅极和晶闸管栅极位于半导体衬底的顶部并且与水平半导体鳍片接触。 存取晶体管是水平半导体鳍片和存取晶体管栅极的至少一部分。 晶闸管是水平半导体鳍片和晶闸管栅极的至少一部分，存取晶体管与晶闸管接触。

公开(公告)号：US20050098794A1

公开(公告)日：2005-05-12

申请号：US11009772

申请日：2004-12-11

申请人： Elgin Quek ,  Pradeep Ramachandramurthy Yelehanka ,  Jia Zheng ,  Tommy Lai ,  Weining Li

发明人： Elgin Quek ,  Pradeep Ramachandramurthy Yelehanka ,  Jia Zheng ,  Tommy Lai ,  Weining Li

IPC分类号： H01L21/332 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/423

CPC分类号： H01L29/66393 ,  H01L27/11

摘要： An integrated circuit structure includes a semiconductor substrate and a thyristor formed thereon. The thyristor has at least four layers, with three P-N junctions therebetween. At least two of the layers are formed horizontally and at least two of the layers are formed vertically. A gate is formed adjacent at least one of the vertically formed layers. An access transistor is formed on the semiconductor substrate, and an interconnect is formed between the thyristor and the access transistor.

摘要翻译： 集成电路结构包括形成在其上的半导体衬底和晶闸管。 晶闸管具有至少四层，其间具有三个P-N结。 至少两层是水平形成的，并且至少两层是垂直形成的。 在至少一个垂直形成的层之间形成栅极。 在半导体衬底上形成存取晶体管，并且在晶闸管和存取晶体管之间形成互连。

公开(公告)号：US20050079674A1

公开(公告)日：2005-04-14

申请号：US10683052

申请日：2003-10-09

申请人： Zia Zheng ,  Pradeep Ramachandramurthy Yelehanka ,  Weining Li

发明人： Zia Zheng ,  Pradeep Ramachandramurthy Yelehanka ,  Weining Li

IPC分类号： H01L21/336 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/115

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11573

摘要： A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming a gate dielectric layer over the semiconductor substrate. The gate dielectric layer is formed in a plurality of thicknesses in a plurality of devices regions over the semiconductor substrate. A second dielectric layer is formed over at least one of the devices regions. A third dielectric layer is formed over at least a portion of the second dielectric layer. Ion traps are then selectively implanted in portions of the second dielectric layer.

摘要翻译： 一种用于制造集成电路结构的方法包括提供半导体衬底并在半导体衬底上形成栅介质层。 栅极电介质层在半导体衬底上的多个器件区域中形成多个厚度。 在至少一个器件区域上形成第二介电层。 在第二电介质层的至少一部分上形成第三电介质层。 然后在第二介电层的部分中选择性地注入离子阱。

公开(公告)号：US20050026343A1

公开(公告)日：2005-02-03

申请号：US10629041

申请日：2003-07-28

申请人： Elgin Quek ,  Jia Zheng ,  Pradeep Yelehanka ,  Weining Li

发明人： Elgin Quek ,  Jia Zheng ,  Pradeep Yelehanka ,  Weining Li

IPC分类号： H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L21/332

CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0657 ,  H01L29/66378 ,  H01L29/66393 ,  H01L29/66795

摘要： A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming a horizontal semiconductor fin on top of the semiconductor substrate. An access transistor gate and a thyristor gate are then formed on top of the semiconductor substrate and in contact with the horizontal semiconductor fin. An access transistor is formed from at least a portion of the horizontal semiconductor fin and the access transistor gate. A thyristor is formed from at least a portion of the horizontal semiconductor fin and the thyristor gate, the access transistor being in contact with the thyristor.

摘要翻译： 一种用于制造集成电路结构的方法包括：在半导体衬底的顶部上提供半导体衬底和形成水平半导体鳍片。 然后在半导体衬底的顶部上形成存取晶体管栅极和晶闸管栅极，并与水平半导体鳍片接触。 存取晶体管由水平半导体鳍片和存取晶体管栅极的至少一部分形成。 晶闸管由水平半导体鳍片和晶闸管栅极的至少一部分形成，存取晶体管与晶闸管接触。

公开(公告)号：US06376298B1

公开(公告)日：2002-04-23

申请号：US09494636

申请日：2000-01-31

申请人： Weining Li ,  Yung-Tao Lin

发明人： Weining Li ,  Yung-Tao Lin

IPC分类号： H01L218234

CPC分类号： H01L21/76897 ,  H01L21/823481

摘要： A method for integrating salicide and self-aligned contact processes in the fabrication of integrated circuits by using a poly cap mask and a special layout technique is described. A pair of gate electrodes and associated source and drain regions are formed overlying a semiconductor substrate wherein nitride spacers are formed on sidewalls of the gate electrodes. A poly-cap layer is deposited overlying the gate electrodes and source and drain regions. The poly-cap layer is selectively removed overlying one of the source and drain regions between the gate electrode pair where a self-aligned contact is to be formed and removed over one of the gate electrode pair. An insulating layer is deposited over the surface of the semiconductor substrate. The planned self-aligned contact opening is made through the insulating layer to the source/drain region to be contacted wherein the contact opening partially overlies the poly-cap layer over the adjacent gate electrode of the pair. The self-aligned contact opening is filled with a conducting layer to complete fabrication of the integrated circuit device.

摘要翻译： 描述了通过使用聚盖掩模和特殊布局技术在集成电路的制造中整合自对准和自对准接触工艺的方法。 一对栅电极和相关的源极和漏极区域形成在半导体衬底上，其中在栅电极的侧壁上形成氮化物间隔物。 覆盖栅电极和源极和漏极区的多晶硅层被沉积。 选择性地去除聚盖层，覆盖栅极电极对之间的源极和漏极区域之一，其中将形成自对准接触并在栅极电极对中的一个上去除。 绝缘层沉积在半导体衬底的表面上。 计划的自对准接触开口通过绝缘层到待接触的源极/漏极区域，其中接触开口部分地覆盖在该对的相邻栅电极上的多晶硅层。 自对准接触开口填充有导电层以完成集成电路器件的制造。