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21.发明申请Method, system, and program product for computing a yield gradient from statistical timing 有权用于从统计时序计算产量梯度的方法，系统和程序产品公开(公告)号：US20070234252A1
公开(公告)日：2007-10-04
申请号：US11358622
申请日：2006-02-21
IPC分类号： G06F17/50
CPC分类号： G06F17/509 , G06F17/5031 , G06F17/504 , G06F2217/10 , G06F2217/12 , Y02P90/265
摘要： The invention provides a method, system, and program product for determining a gradient of a parametric yield of an integrated circuit with respect to parameters of a delay of an edge of a timing graph of the circuit. A first aspect of the invention provides a method for determining a gradient of a parametric yield of an integrated circuit with respect to parameters of a delay of an edge of a timing graph of the circuit, the method comprising: conducting a statistical timing analysis; expressing a statistical circuit delay in terms of a delay of the edge; and computing a gradient of the statistical circuit delay with respect to parameters of the delay of the edge.
摘要翻译： 本发明提供了一种方法，系统和程序产品，用于相对于电路的时序图的边沿的延迟的参数来确定集成电路的参数收益率的梯度。 本发明的第一方面提供了一种用于根据电路的时序图的边沿的延迟的参数来确定集成电路的参数收益率的梯度的方法，所述方法包括：进行统计时序分析; 根据边缘的延迟表示统计电路延迟; 以及计算相对于边缘的延迟的参数的统计电路延迟的梯度。
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22.发明申请METHOD AND APPARATUS FOR SELECTING VOLTAGE AND FREQUENCY LEVELS FOR USE IN AT-SPEED TESTING 失效用于选择在速度测试中使用的电压和频率水平的方法和装置公开(公告)号：US20110191055A1
公开(公告)日：2011-08-04
申请号：US12696902
申请日：2010-01-29
摘要： In one embodiment, the invention is a method and apparatus for selecting voltage and frequency levels for use in at-speed testing. One embodiment of a method for selecting a set of test conditions with which to test an integrated circuit chip includes formulating a statistical optimization problem and obtaining a solution to the statistical optimization problem, where the solution is the set of test conditions.
摘要翻译： 在一个实施例中，本发明是用于选择在速度测试中使用的电压和频率水平的方法和装置。 用于选择用于测试集成电路芯片的一组测试条件的方法的一个实施例包括制定统计优化问题并获得统计优化问题的解决方案，其中解是测试条件集合。
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公开(公告)号：US08510696B2
公开(公告)日：2013-08-13
申请号：US13422637
申请日：2012-03-16
IPC分类号： G06F17/50
CPC分类号： G06F17/50
摘要： Solutions for ordering of statistical correlated quantities are disclosed. In one aspect, a method includes timing a plurality of paths in an integrated circuit to determine a set of timing quantities associated with each of the plurality of paths; determining a most critical timing quantity in the set of timing quantities; forming a tiered timing quantity arrangement for ordering a plurality of timing quantities in the set of timing quantities; removing the most critical timing quantity from the set of timing quantities and placing the most critical timing quantity in an uppermost available tier of the tiered timing quantity arrangement; and repeating the determining, forming and removing for the set of timing quantities excluding the removed most critical timing quantity.
摘要翻译： 公布统计相关数量排序的解决方案。 在一个方面，一种方法包括对集成电路中的多个路径进行定时以确定与多个路径中的每一条相关联的一组定时量; 确定所述一组定时数量中最关键的定时数量; 形成用于在所述一组定时量中排序多个定时量的分层定时量排列; 从所述定时量集合中去除最关键的定时数量，并将最关键的定时数量置于分层定时数量排列的最上层可用层; 并且重复确定，形成和去除不包括去除的最关键定时量的一组定时量。
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公开(公告)号：US20090150844A1
公开(公告)日：2009-06-11
申请号：US11954138
申请日：2007-12-11
申请人： Vikram Iyengar , David E. Lackey , Subbayyan Venkatesan , Chandramouli Visweswariah , Jinjun Xiong
发明人： Vikram Iyengar , David E. Lackey , Subbayyan Venkatesan , Chandramouli Visweswariah , Jinjun Xiong
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method of critical path selection provides a set of paths that initially contains no paths. A timing tool is used to identify potential critical paths of an integrated circuit design. Each potential critical path is evaluated and the potential critical path is added to the set of paths if logic devices within the potential critical path are shared by less than a predetermined number of critical paths within the set of paths. This evaluating and adding process is repeated for each of the potential critical paths until all of the potential critical paths have been evaluated. Then, the potential critical paths within the set of paths can be output.
摘要翻译： 关键路径选择的方法提供了一组最初不包含路径的路径。 定时工具用于识别集成电路设计的潜在关键路径。 如果潜在的关键路径内的逻辑设备被小于路径集合内预定数量的关键路径共享，则评估每个潜在的关键路径并将潜在的关键路径添加到路径集合。 对于每个潜在的关键路径重复该评估和添加过程，直到所有潜在的关键路径都被评估为止。 然后，可以输出该组路径内的潜在关键路径。
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25.发明授权Method and apparatus for selecting voltage and frequency levels for use in at-speed testing 失效用于选择用于速度测试的电压和频率电平的方法和装置公开(公告)号：US08676536B2
公开(公告)日：2014-03-18
申请号：US12696902
申请日：2010-01-29
摘要： In one embodiment, the invention is a method and apparatus for selecting voltage and frequency levels for use in at-speed testing. One embodiment of a method for selecting a set of test conditions with which to test an integrated circuit chip includes formulating a statistical optimization problem and obtaining a solution to the statistical optimization problem, where the solution is the set of test conditions.
摘要翻译： 在一个实施例中，本发明是用于选择在速度测试中使用的电压和频率水平的方法和装置。 用于选择用于测试集成电路芯片的一组测试条件的方法的一个实施例包括制定统计优化问题并获得统计优化问题的解决方案，其中解是测试条件集合。
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公开(公告)号：US08266565B2
公开(公告)日：2012-09-11
申请号：US12696186
申请日：2010-01-29
IPC分类号： G06F17/50
CPC分类号： G06F17/50
摘要： Solutions for ordering of statistical correlated quantities are disclosed. In one aspect, a method includes timing a plurality of paths in an integrated circuit to determine a set of timing quantities associated with each of the plurality of paths; determining a most critical timing quantity in the set of timing quantities; forming a tiered timing quantity arrangement for ordering a plurality of timing quantities in the set of timing quantities; removing the most critical timing quantity from the set of timing quantities and placing the most critical timing quantity in an uppermost available tier of the tiered timing quantity arrangement; and repeating the determining, forming and removing for the set of timing quantities excluding the removed most critical timing quantity.
摘要翻译： 公布统计相关数量排序的解决方案。 在一个方面，一种方法包括对集成电路中的多个路径进行定时以确定与多个路径中的每一条相关联的一组定时量; 确定所述一组定时数量中最关键的定时数量; 形成用于在所述一组定时量中排序多个定时量的分层定时量排列; 从所述定时量集合中去除最关键的定时数量，并将最关键的定时数量置于分层定时数量排列的最上层可用层; 并且重复确定，形成和去除不包括去除的最关键定时量的一组定时量。
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公开(公告)号：US20120192136A1
公开(公告)日：2012-07-26
申请号：US13422637
申请日：2012-03-16
IPC分类号： G06F9/455
CPC分类号： G06F17/50
摘要： Solutions for ordering of statistical correlated quantities are disclosed. In one aspect, a method includes timing a plurality of paths in an integrated circuit to determine a set of timing quantities associated with each of the plurality of paths; determining a most critical timing quantity in the set of timing quantities; forming a tiered timing quantity arrangement for ordering a plurality of timing quantities in the set of timing quantities; removing the most critical timing quantity from the set of timing quantities and placing the most critical timing quantity in an uppermost available tier of the tiered timing quantity arrangement; and repeating the determining, forming and removing for the set of timing quantities excluding the removed most critical timing quantity.
摘要翻译： 公布统计相关数量排序的解决方案。 在一个方面，一种方法包括对集成电路中的多个路径进行定时以确定与多个路径中的每一条相关联的一组定时量; 确定所述一组定时数量中最关键的定时数量; 形成用于在所述一组定时量中排序多个定时量的分层定时量排列; 从所述定时量集合中去除最关键的定时数量，并将最关键的定时数量置于分层定时数量排列的最上层可用层; 并且重复确定，形成和去除不包括去除的最关键定时量的一组定时量。
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公开(公告)号：US20110191730A1
公开(公告)日：2011-08-04
申请号：US12696186
申请日：2010-01-29
IPC分类号： G06F17/50
CPC分类号： G06F17/50
摘要： Solutions for ordering of statistical correlated quantities are disclosed. In one aspect, a method includes timing a plurality of paths in an integrated circuit to determine a set of timing quantities associated with each of the plurality of paths; determining a most critical timing quantity in the set of timing quantities; forming a tiered timing quantity arrangement for ordering a plurality of timing quantities in the set of timing quantities; removing the most critical timing quantity from the set of timing quantities and placing the most critical timing quantity in an uppermost available tier of the tiered timing quantity arrangement; and repeating the determining, forming and removing for the set of timing quantities excluding the removed most critical timing quantity.
摘要翻译： 公布统计相关数量排序的解决方案。 在一个方面，一种方法包括对集成电路中的多个路径进行定时以确定与多个路径中的每一条相关联的一组定时量; 确定所述一组定时数量中最关键的定时数量; 形成用于在所述一组定时量中排序多个定时量的分层定时量排列; 从所述定时量集合中去除最关键的定时数量，并将最关键的定时数量置于分层定时数量排列的最上层可用层; 并且重复确定，形成和去除不包括去除的最关键定时量的一组定时量。
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29.发明授权System and method for accommodating non-Gaussian and non-linear sources of variation in statistical static timing analysis 有权用于在统计静态时序分析中适应非高斯和非线性变化源的系统和方法公开(公告)号：US07293248B2
公开(公告)日：2007-11-06
申请号：US11056850
申请日：2005-02-11
CPC分类号： G06F17/5031
摘要： There is provided a system and method for statistical timing analysis of an electrical circuit. The system includes at least one parameter input, a statistical static timing analyzer, and at least one output. The at least one parameter input is for receiving parameters of the electrical circuit. At least one of the parameters has at least one of a non-Gaussian probability distribution and a non-linear delay effect. The statistical static timing analyzer is for calculating at least one of a signal arrival time and a signal required time for the electrical circuit using the at least one parameter. The at least one output is for outputting the at least one of the signal arrival time and the signal required time.
摘要翻译： 提供了一种用于电路的统计时序分析的系统和方法。 该系统包括至少一个参数输入，统计静态时序分析器和至少一个输出。 至少一个参数输入用于接收电路的参数。 至少一个参数具有非高斯概率分布和非线性延迟效应中的至少一个。 统计静态时序分析器用于使用至少一个参数来计算电路的信号到达时间和信号所需时间中的至少一个。 至少一个输出用于输出信号到达时间和信号所需时间中的至少一个。
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30.发明申请System and method for accommodating non-gaussian and non-linear sources of variation in statistical static timing analysis 有权用于在统计静态时序分析中调节非高斯和非线性变化源的系统和方法公开(公告)号：US20060085775A1
公开(公告)日：2006-04-20
申请号：US11056850
申请日：2005-02-11
CPC分类号： G06F17/5031
摘要： There is provided a system and method for statistical timing analysis of an electrical circuit. The system includes at least one parameter input, a statistical static timing analyzer, and at least one output. The at least one parameter input is for receiving parameters of the electrical circuit. At least one of the parameters has at least one of a non-Gaussian probability distribution and a non-linear delay effect. The statistical static timing analyzer is for calculating at least one of a signal arrival time and a signal required time for the electrical circuit using the at least one parameter. The at least one output is for outputting the at least one of the signal arrival time and the signal required time.
摘要翻译： 提供了一种用于电路的统计时序分析的系统和方法。 该系统包括至少一个参数输入，统计静态时序分析器和至少一个输出。 至少一个参数输入用于接收电路的参数。 至少一个参数具有非高斯概率分布和非线性延迟效应中的至少一个。 统计静态时序分析器用于使用至少一个参数来计算电路的信号到达时间和信号所需时间中的至少一个。 至少一个输出用于输出信号到达时间和信号所需时间中的至少一个。
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