公开(公告)号：US09058034B2

公开(公告)日：2015-06-16

申请号：US13570285

申请日：2012-08-09

申请人： Jeanne P. Bickford ,  Peter A. Habitz ,  Vikram Iyengar ,  Jinjun Xiong

发明人： Jeanne P. Bickford ,  Peter A. Habitz ,  Vikram Iyengar ,  Jinjun Xiong

IPC分类号： G06F17/50 ,  G05B19/418

CPC分类号： G05B19/41875 ,  G05B2219/32182 ,  G05B2219/32187 ,  G05B2219/32208 ,  G05B2219/37224 ,  Y02P80/30 ,  Y02P90/22

摘要： Disclosed are embodiments of a method, system and computer program product for optimizing integrated circuit product yield by re-centering the manufacturing line and, optionally, adjusting wafer-level chip dispositioning rules based on the results of post-manufacture (e.g., wafer-level or module-level) performance path testing. In the embodiments, a correlation is made between in-line parameter measurements and performance measurements acquired during the post-manufacture performance path testing. Then, based on this correlation, the manufacturing line can be re-centered. Optionally, an additional correlation is made between performance measurements acquired during wafer-level performance testing and performance measurements acquired particularly during module-level performance path testing and, based on this additional correlation, adjustments can be made to the wafer-level chip dispositioning rules to further minimize yield loss.

摘要翻译： 公开了用于通过使生产线重新对中来优化集成电路产品产量的方法，系统和计算机程序产品的实施例，并且可选地，基于后期制造的结果调整晶片级芯片布置规则（例如，晶片级 或模块级）性能路径测试。 在实施例中，在后续制造性能路径测试期间获得的在线参数测量和性能测量之间进行相关。 然后，基于这种相关性，生产线可以重新居中。 可选地，在晶片级性能测试期间获得的性能测量和特别在模块级性能路径测试期间获得的性能测量之间进行附加的相关性，并且基于该附加相关性，可以对晶片级芯片布置规则进行调整 进一步降低产量损失。

公开(公告)号：US08825433B2

公开(公告)日：2014-09-02

申请号：US13241651

申请日：2011-09-23

申请人： Konda R. Baalaji ,  Malede W. Berhanu ,  Vikram Iyengar ,  Douglas C. Pricer

发明人： Konda R. Baalaji ,  Malede W. Berhanu ,  Vikram Iyengar ,  Douglas C. Pricer

IPC分类号： G06F19/00 ,  G01R31/28

CPC分类号： G01R31/31726

摘要： A method and system is provided for automatically generating valid at speed structural test (ASST) test groups. The method includes loading a netlist for an integrated circuit into a processor. The method further includes determining a plurality of clock domain crossings between a plurality of clock domains within the integrated circuit. The method further includes generating a first test group. The method further includes adding a first clock domain of the plurality of clock domains to the first test group. The method further includes adding a second clock domain of the plurality of clock domains to the first test group when the second clock domain does not have a clock domain crossing into the first clock domain.

摘要翻译： 提供了一种自动生成有效的速度结构测试（ASST）测试组的方法和系统。 该方法包括将集成电路的网表加载到处理器中。 该方法还包括确定集成电路内的多个时钟域之间的多个时钟域交叉。 该方法还包括产生第一测试组。 该方法还包括将多个时钟域的第一时钟域添加到第一测试组。 该方法还包括当第二时钟域不具有与第一时钟域交叉的时钟域时，将多个时钟域的第二时钟域添加到第一测试组。

公开(公告)号：US08538718B2

公开(公告)日：2013-09-17

申请号：US12967885

申请日：2010-12-14

申请人： Gary D. Grise ,  Vikram Iyengar ,  Douglas E. Sprague ,  Mark R. Taylor

发明人： Gary D. Grise ,  Vikram Iyengar ,  Douglas E. Sprague ,  Mark R. Taylor

IPC分类号： G06F19/00

CPC分类号： G01R31/31726 ,  G01R31/31922

摘要： A method of grouping clock domains includes: separating a plurality of test clocks into a plurality of domain groups by adding to each respective one of the plurality of domain groups those test clocks that originate from a same clock source and have a unique clock divider ratio; sorting the domain groups in decreasing order of size; and creating a plurality of parts by adding the respective one of the plurality of domain groups to a first one of the plurality of parts in which already present test clocks have a different clock source, and creating a new part and adding the respective one of the plurality of domain groups to the new part when test clocks present in the respective one of the plurality of domain groups originate from a respective same clock source and have a different clock divider ratio as test clocks present in all previously-created parts.

摘要翻译： 一种对时钟域进行分组的方法包括：通过向多个域组中的每个相应的一个组分配来自相同时钟源的那些测试时钟并具有唯一的时钟分频比，将多个测试时钟分离成多个域组; 按照大小顺序排列域组; 以及通过将多个域组中的相应一个组合添加到已经存在的测试时钟具有不同时钟源的多个部分中的第一部分来创建多个部分，并且创建新部分并将相应的一个 当存在于多个域组中的相应一个域组中的相应一个域组中的测试时钟源自相应的相同时钟源并且具有不同的时钟分频比作为存在于所有先前创建的部分中的测试时钟时，多个域组到新部分。

公开(公告)号：US08176362B2

公开(公告)日：2012-05-08

申请号：US12053642

申请日：2008-03-24

申请人： Monty M Denneau ,  Vikram Iyengar ,  Phillip J. Nigh

发明人： Monty M Denneau ,  Vikram Iyengar ,  Phillip J. Nigh

IPC分类号： G06F11/00

CPC分类号： G06F11/008 ,  G06F11/2025 ,  G06F11/2028 ,  G06F11/2242 ,  G06F11/3409

摘要： A multiprocessor system comprising a plurality of processors is disclosed. The plurality of processors includes a first processor including first monitor on-chip and a second processor including a including a second monitor on-chip. The first monitor on-chip is configured to measure load on the second processor and the second monitor on-chip is configured to measure load on the first processor. The first monitor on-chip is configured to cause the second monitor on-chip to perform a self-test on the second processor if the load on the second processor is below a second processor load threshold value and the second monitor on-chip is configured to cause the first monitor on-chip to perform a self-test on the first processor if the load on the first processor is below first processor load threshold value.

摘要翻译： 公开了一种包括多个处理器的多处理器系统。 多个处理器包括第一处理器，其包括片上第一监视器和第二处理器，其包括在片上包括第二监视器的第二处理器。 第一个片上显示器被配置为测量第二处理器上的负载，并且片上第二个监视器被配置为测量第一处理器上的负载。 如果第二处理器上的负载低于第二处理器负载阈值并且片上第二监视器被配置，片上的第一个监视器被配置为使片上的第二监视器在第二处理器上执行自检 如果第一处理器上的负载低于第一处理器负载阈值，则使片上的第一个监视器在第一处理器上执行自检。

公开(公告)号：US07793176B2

公开(公告)日：2010-09-07

申请号：US11696981

申请日：2007-04-05

申请人： Gary D. Grise ,  David J. Hathaway ,  Vikram Iyengar

发明人： Gary D. Grise ,  David J. Hathaway ,  Vikram Iyengar

IPC分类号： G01R31/28

CPC分类号： G01R31/31715 ,  G01R31/31707 ,  G01R31/318328

摘要： A method for automatically generating test patterns for digital logic circuitry using an automatic test pattern generation tool. The method includes generating test patterns and applying faulty behavior to various paths within the digital logic circuitry. As each circuit path is tested, tested circuit nodes along the circuit path are marked as “exercised.” Subsequent test paths are assembled by avoiding marked circuit nodes. In this manner, coverage of paths tested may be increased and many circuit nodes can be tested efficiently.

摘要翻译： 一种使用自动测试图案生成工具自动生成数字逻辑电路测试图案的方法。 该方法包括生成测试模式并将故障行为应用于数字逻辑电路内的各种路径。 随着每个电路路径的测试，沿着电路路径的测试电路节点被标记为“行使”。随后的测试路径通过避免标记的电路节点进行组装。 以这种方式，可以增加测试路径的覆盖范围，并且可以有效地测试许多电路节点。

公开(公告)号：US20090106608A1

公开(公告)日：2009-04-23

申请号：US11874972

申请日：2007-10-19

申请人： Gary D. Grise ,  Vikram Iyengar ,  David E. Lackey ,  Mark R. Taylor

发明人： Gary D. Grise ,  Vikram Iyengar ,  David E. Lackey ,  Mark R. Taylor

IPC分类号： G01R31/28

CPC分类号： G01R31/318594 ,  G01R31/318541

摘要： An apparatus for selectively implementing launch-off-scan capability in at-speed testing of integrated circuit devices includes a control device configured to selectively disable a master clock signal of a latch structure under test such that a pulse sequence of a system clock signal results in a slave-master-slave clock pulse sequence in the latch structure under test; wherein the control device utilizes the system clock signal as an input thereto and operates in a self-resetting fashion that is timing independent with respect to a scan chain.

摘要翻译： 一种用于在集成电路装置的高速测试中选择性地实施发射扫描能力的装置包括控制装置，其被配置为选择性地禁用被测闩锁结构的主时钟信号，使得系统时钟信号的脉冲序列导致 被锁存结构中的从主从主时钟脉冲序列; 其中所述控制装置利用所述系统时钟信号作为其输入，并以相对于扫描链定时无关的自复位方式操作。

公开(公告)号：US20080270953A1

公开(公告)日：2008-10-30

申请号：US11741164

申请日：2007-04-27

申请人： Eric A. Foreman ,  Gary D. Grise ,  Peter A. Habitz ,  Vikram Iyengar ,  David E. Lackey ,  Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

发明人： Eric A. Foreman ,  Gary D. Grise ,  Peter A. Habitz ,  Vikram Iyengar ,  David E. Lackey ,  Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/10

摘要： Methods, systems and program products for evaluating an IC chip are disclosed. In one embodiment, the method includes running a statistical static timing analysis (SSTA) of a full IC chip design; creating at-functional-speed test (AFST) robust paths for an IC chip, the created robust paths representing a non-comprehensive list of AFST robust paths for the IC chip; and re-running the SSTA with the SSTA delay model setup based on the created robust paths. A process coverage is calculated for evaluation from the SSTA runnings; and a particular IC chip is evaluated based on the process coverage.

摘要翻译： 公开了用于评估IC芯片的方法，系统和程序产品。 在一个实施例中，该方法包括运行全IC芯片设计的统计静态时序分析（SSTA）; 创建用于IC芯片的功能速度测试（AFST）鲁棒路径，所创建的鲁棒路径表示IC芯片的AFST鲁棒路径的非全面列表; 并基于创建的鲁棒路径，使用SSTA延迟模型设置重新运行SSTA。 计算过程覆盖率用于从SSTA运行中进行评估; 并且基于处理覆盖来评估特定的IC芯片。

公开(公告)号：US20080222472A1

公开(公告)日：2008-09-11

申请号：US11684242

申请日：2007-03-09

申请人： Gary D. Grise ,  Vikram Iyengar ,  Mark R. Taylor

发明人： Gary D. Grise ,  Vikram Iyengar ,  Mark R. Taylor

IPC分类号： G01R31/28

CPC分类号： G01R31/318307

摘要： A method for automatically generating test patterns for an IC device includes initially generating a subset of available test patterns according to each of a plurality of test constraints for the IC device, determining an incremental amount of total test coverage of the IC device attributable to each of the test constraints as a result of the initially generated subset of test patterns therefor; determining the test constraint initially providing the largest amount of incremental test coverage, and thereafter generating another subset of test patterns therefor; and iteratively determining the current test constraint providing the largest amount of incremental test coverage, and continuing to generate additional test patterns therefor until one or more test exit criteria is reached.

摘要翻译： 一种用于自动生成用于IC器件的测试图案的方法包括：根据IC器件的多个测试约束中的每一个，初始地生成可用测试图案的子集，确定归属于每个IC器件的IC器件的总测试覆盖的增量 作为最初生成的测试模式子集的结果的测试约束; 确定最初提供最大量的增量测试覆盖的测试约束，然后生成另一个测试模式子集; 并迭代地确定提供最大量的增量测试覆盖的当前测试约束，并且继续生成附加的测试模式，直到达到一个或多个测试退出标准。

公开(公告)号：US09043180B2

公开(公告)日：2015-05-26

申请号：US13369642

申请日：2012-02-09

申请人： Vikram Iyengar ,  Animesh Khare ,  Kenneth Pichamuthu

发明人： Vikram Iyengar ,  Animesh Khare ,  Kenneth Pichamuthu

IPC分类号： G01N33/48 ,  G01R31/3185

CPC分类号： G01R31/318314 ,  G01R31/318307 ,  G01R31/318575

摘要： Aspects of the invention provide for reducing power consumption during manufacturing testing of an IC. In one embodiment, aspects of the invention include a method for reducing power consumption during a manufacturing test of an integrated circuit (IC), the method including: providing a plurality of domains, each domain associated with a clock phase; grouping, based on each domain, a first plurality of scan chains into a first test group; grouping, based on each domain, a second plurality of scan chains into a second test group, wherein the grouping of the first test group and of the second test group includes determining which domains can be tested simultaneously; and performing the manufacturing test of the IC.

摘要翻译： 本发明的方面提供了在IC的制造测试期间降低功耗。 在一个实施例中，本发明的方面包括一种用于在集成电路（IC）的制造测试期间降低功耗的方法，所述方法包括：提供多个域，每个域与时钟相关联; 将基于每个域的第一多个扫描链分组成第一测试组; 基于每个域将第二多个扫描链分组成第二测试组，其中第一测试组和第二测试组的分组包括确定可以同时测试哪些结构域; 并进行IC的制造测试。

公开(公告)号：US08543966B2

公开(公告)日：2013-09-24

申请号：US13294210

申请日：2011-11-11

申请人： Jeanne P. Bickford ,  Peter A. Habitz ,  Vikram Iyengar ,  David E. Lackey ,  Jinjun Xiong

发明人： Jeanne P. Bickford ,  Peter A. Habitz ,  Vikram Iyengar ,  David E. Lackey ,  Jinjun Xiong

IPC分类号： G06F11/22 ,  G06F17/50

CPC分类号： G01R31/31726 ,  G01R31/318541

摘要： A method of test path selection and test program generation for performance testing integrated circuits. The method includes identifying clock domains having multiple data paths of an integrated circuit design having multiple clock domains; selecting, from the data paths, critical paths for each clock domain of the multiple clock domains; using a computer, for each clock domain of the multiple clock domain, selecting the sensitizable paths of the critical paths; for each clock domain of the multiple clock domain, selecting test paths from the sensitizable critical paths; and using a computer, creating a test program to performance test the test paths.

摘要翻译： 一种用于性能测试集成电路的测试路径选择和测试程序生成的方法。 该方法包括识别具有具有多个时钟域的集成电路设计的多个数据路径的时钟域; 从数据路径中选择多个时钟域的每个时钟域的关键路径; 使用计算机，对于多个时钟域的每个时钟域，选择关键路径的可敏化路径; 对于多个时钟域的每个时钟域，从敏感关键路径中选择测试路径; 并使用计算机，创建测试程序来测试测试路径。