公开(公告)号：US20130113042A1

公开(公告)日：2013-05-09

申请号：US13288047

申请日：2011-11-03

申请人： Chih-Ching Wang ,  Jon-Hsu Ho ,  Ching-Fang Huang ,  Wen-Hsing Hsieh ,  Tsung-Hsing Yu ,  Yi-Ming Sheu ,  Ken-Ichi Goto ,  Zhiqiang Wu

发明人： Chih-Ching Wang ,  Jon-Hsu Ho ,  Ching-Fang Huang ,  Wen-Hsing Hsieh ,  Tsung-Hsing Yu ,  Yi-Ming Sheu ,  Ken-Ichi Goto ,  Zhiqiang Wu

IPC分类号： H01L27/092 ,  H01L21/336

CPC分类号： H01L29/7855 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/785

摘要： A multi-gate semiconductor device and method for forming the same. A multi-gate semiconductor device is formed including a first fin of a first transistor formed on a semiconductor substrate having a first dopant type. The first transistor has a doped channel region of the first dopant type. The device also includes a second fin of a second transistor formed on the first dopant type semiconductor substrate. The second transistor has a doped channel region of a second dopant type. The device further includes a gate electrode layer of the second dopant type formed over the channel region of the first fin and a gate electrode layer of the first dopant type formed over the channel region of the second fin.

摘要翻译： 一种多栅半导体器件及其制造方法。 形成多栅半导体器件，其包括形成在具有第一掺杂剂类型的半导体衬底上的第一晶体管的第一鳍。 第一晶体管具有第一掺杂剂类型的掺杂沟道区。 该器件还包括形成在第一掺杂剂型半导体衬底上的第二晶体管的第二鳍。 第二晶体管具有第二掺杂剂类型的掺杂沟道区。 该器件还包括形成在第一鳍片的沟道区域上的第二掺杂剂类型的栅极电极层和形成在第二鳍片的沟道区域上的第一掺杂剂类型的栅极电极层。

公开(公告)号：US20100123203A1

公开(公告)日：2010-05-20

申请号：US12273409

申请日：2008-11-18

申请人： Krishna Kumar Bhuwalka ,  Yi-Ming Sheu ,  Carlos H. Diaz

发明人： Krishna Kumar Bhuwalka ,  Yi-Ming Sheu ,  Carlos H. Diaz

IPC分类号： H01L29/78

CPC分类号： H01L29/7391 ,  H01L29/66356

摘要： A semiconductor device includes a channel region; a gate dielectric over the channel region; and a gate electrode over the gate dielectric. A first source/drain region is adjacent the gate dielectric, wherein the first source/drain region is a semiconductor region and of a first conductivity type. A second source/drain region is on an opposite side of the channel region than the first source/drain region, wherein the second source/drain region is a metal region. A pocket region of a second conductivity type opposite the first conductivity type is horizontally between the channel region and the second source/drain region.

摘要翻译： 半导体器件包括沟道区; 沟道区上的栅极电介质; 以及在栅极电介质上的栅电极。 第一源极/漏极区域与栅极电介质相邻，其中第一源极/漏极区域是半导体区域并且具有第一导电类型。 第二源极/漏极区域在沟道区域的与第一源极/漏极区域相反的一侧上，其中第二源极/漏极区域是金属区域。 与第一导电类型相反的第二导电类型的口袋区域在沟道区域和第二源极/漏极区域之间是水平的。

公开(公告)号：US20080290412A1

公开(公告)日：2008-11-27

申请号：US11751959

申请日：2007-05-22

申请人： Chih-Chiang Wang ,  Yi-Ming Sheu ,  Ying-Shiou Lin

发明人： Chih-Chiang Wang ,  Yi-Ming Sheu ,  Ying-Shiou Lin

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/1083 ,  H01L29/66636

摘要： An apparatus comprising a substrate of first dopant type and first dopant concentration; pocket regions in the substrate and having the first dopant type and a second dopant concentration greater than the first dopant concentration; a gate stack over the substrate and laterally between the pocket regions; first and second source/drain regions on opposing sides of the gate stack and vertically between the gate stack and the pocket regions, the first and second source/drain regions having a second dopant type opposite the first dopant type and a third dopant concentration; and third and fourth source/drain regions having the second dopant type and a fourth dopant concentration that is greater than the third dopant concentration, wherein the pocket regions are between the third and fourth source/drain regions, and the third and fourth source/drain regions are vertically between the first and second source/drain regions and a bulk portion of the substrate.

摘要翻译： 一种装置，包括第一掺杂剂型和第一掺杂剂浓度的衬底; 并且具有大于第一掺杂剂浓度的第一掺杂剂类型和第二掺杂剂浓度; 在所述衬底上方的栅堆叠，并且在所述袋区域之间横向; 第一和第二源极/漏极区域在栅极堆叠的相对侧上并且垂直地在栅极堆叠层与凹穴区域之间，第一和第二源极/漏极区域具有与第一掺杂剂类型相反的第二掺杂剂类型和第三掺杂剂浓度; 以及具有大于第三掺杂剂浓度的第二掺杂剂类型和第四掺杂剂浓度的第三和第四源极/漏极区域，其中所述穴状区域在第三和第四源极/漏极区域之间，并且第三和第四源极/漏极 区域在第一和第二源极/漏极区域之间以及基板的主体部分之间是垂直的。

公开(公告)号：US07371629B2

公开(公告)日：2008-05-13

申请号：US10314689

申请日：2002-12-09

申请人： Chu-Yun Fu ,  Chi-Hsun Hsieh ,  Yi-Ming Sheu ,  Syun-Ming Jang

发明人： Chu-Yun Fu ,  Chi-Hsun Hsieh ,  Yi-Ming Sheu ,  Syun-Ming Jang

IPC分类号： H01L21/8237

CPC分类号： H01L21/0217 ,  H01L21/02274 ,  H01L21/28247 ,  H01L21/3185 ,  H01L21/823814 ,  H01L21/823835

摘要： A method is provided for improving Idsat in NMOS and PMOS transistors. A silicon nitride etch stop layer is deposited by a PECVD technique on STI and silicide regions and on sidewall spacers during a MOSFET manufacturing scheme. A dielectric layer is formed on the nitride and then contact holes are fabricated through the dielectric layer and nitride layer to silicide regions and are filled with a metal. For NMOS transistors, silane and NH3 flow rates and a 400° C. temperature are critical in improving NMOS short channel Idsat. Hydrogen content in the nitride is increased by higher NH3 and SiH4 flow rates but does not significantly degrade HCE and Vt. With PMOS transistors, deposition temperature is increased to 550° C. to reduce hydrogen content and improve HCE and Vt stability.

摘要翻译： 提供了一种用于改善NMOS和PMOS晶体管中的Idsat的方法。 在MOSFET制造方案中，通过PECVD技术在STI和硅化物区域和侧壁间隔物上沉积氮化硅蚀刻停止层。 在氮化物上形成介电层，然后通过电介质层和氮化物层到硅化物区域制造接触孔，并填充金属。 对于NMOS晶体管，硅烷和NH 3 3流速和400℃的温度对于改善NMOS短沟道Idsat至关重要。 氮化物中的氢含量通过较高的NH 3和SiH 4 O 3流速而增加，但不会显着降低HCE和Vt。使用PMOS晶体管，沉积温度增加到550° C.降低氢含量，提高HCE和Vt稳定性。

公开(公告)号：US20060033158A1

公开(公告)日：2006-02-16

申请号：US11255389

申请日：2005-10-21

申请人： Carlos Diaz ,  Yi-Ming Sheu ,  Syun-Ming Jang ,  Hun-Jan Tao ,  Fu-Liang Yang

发明人： Carlos Diaz ,  Yi-Ming Sheu ,  Syun-Ming Jang ,  Hun-Jan Tao ,  Fu-Liang Yang

IPC分类号： H01L29/78

CPC分类号： H01L29/66772 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/78621 ,  H01L29/78654

摘要： A method for forming a field effect transistor device employs a self-aligned etching of a semiconductor substrate to form a recessed channel region in conjunction with a pair of raised source/drain regions. The method also provides for forming and thermally annealing the pair of source/drain regions prior to forming a pair of lightly doped extension regions within the field effect transistor device. In accord with the foregoing features, the field effect transistor device is fabricated with enhanced performance.

摘要翻译： 用于形成场效应晶体管器件的方法采用半导体衬底的自对准蚀刻以与一对凸起的源极/漏极区域结合形成凹陷沟道区域。 该方法还提供了在场效应晶体管器件内形成一对轻掺杂的延伸区域之前，对成对的源/漏区进行形成和热退火。 根据上述特征，以增强的性能制造场效应晶体管器件。

公开(公告)号：US06673683B1

公开(公告)日：2004-01-06

申请号：US10291029

申请日：2002-11-07

申请人： Yi-Ming Sheu ,  Yi-Ling Chan ,  Da-Wen Lin ,  Wan-Yih Lien ,  Carlos H. Diaz

发明人： Yi-Ming Sheu ,  Yi-Ling Chan ,  Da-Wen Lin ,  Wan-Yih Lien ,  Carlos H. Diaz

IPC分类号： H01L21336

CPC分类号： H01L29/66553 ,  H01L29/66545 ,  H01L29/6659

摘要： A method for forming a field effect transistor device within a semiconductor product employs a patterned dummy layer first as an ion implantation mask layer when forming a pair of source/drain regions, and then as a mandrel layer for forming a pair of patterned sacrificial layers which define an aperture of linewidth and location corresponding to the patterned dummy layer. A pair of sacrificial spacer layers and a gate electrode are then formed self-aligned within the aperture. The pair of patterned sacrificial layers and the pair of sacrificial spacer layers are then stripped and the gate electrode is employed as a mask for ion implanting forming a pair of lightly doped extension regions partially overlapping the pair of source/drain regions within the semiconductor substrate.

摘要翻译： 在半导体产品中形成场效应晶体管器件的方法当形成一对源极/漏极区域时首先使用图案化虚拟层作为离子注入掩模层，然后作为用于形成一对图案化牺牲层的心轴层， 限定对应于图案化虚拟层的线宽和位置的孔径。 然后在孔内自对准地形成一对牺牲间隔层和栅电极。 然后剥去一对图案化牺牲层和一对牺牲隔离层，并且使用栅电极作为用于离子注入的掩模，形成与半导体衬底内的一对源/漏区部分重叠的一对轻掺杂的延伸区。

公开(公告)号：US06670226B2

公开(公告)日：2003-12-30

申请号：US10094460

申请日：2002-03-08

申请人： Yo-Sheng Lin ,  Yi-Ming Sheu ,  Da-Wen Lin ,  Chi-Hsun Hsieh

发明人： Yo-Sheng Lin ,  Yi-Ming Sheu ,  Da-Wen Lin ,  Chi-Hsun Hsieh

IPC分类号： H01L218238

CPC分类号： H01L21/823842 ,  H01L21/32115 ,  H01L21/3212

摘要： Within a method for fabricating a semiconductor integrated circuit microelectronic fabrication, there is employed a planarizing method for forming, in a self aligned fashion, a patterned second gate electrode material layer laterally adjacent but not over a patterned first gate electrode material layer, such that upon further patterning of the patterned first gate electrode material layer and the patterned second gate electrode material layer there may be formed a first gate electrode over a first active region of a semiconductor substrate and a second gate electrode over a laterally adjacent second active region of the semiconductor substrate. The method is particularly useful within the context of complementary metal oxide semiconductor (CMOS) semiconductor integrated circuit microelectronic fabrications.

公开(公告)号：US08587075B2

公开(公告)日：2013-11-19

申请号：US12273409

申请日：2008-11-18

申请人： Krishna Kumar Bhuwalka ,  Yi-Ming Sheu ,  Carlos H. Diaz

发明人： Krishna Kumar Bhuwalka ,  Yi-Ming Sheu ,  Carlos H. Diaz

IPC分类号： H01L29/78

CPC分类号： H01L29/7391 ,  H01L29/66356

摘要： A semiconductor device includes a channel region; a gate dielectric over the channel region; and a gate electrode over the gate dielectric. A first source/drain region is adjacent the gate dielectric, wherein the first source/drain region is a semiconductor region and of a first conductivity type. A second source/drain region is on an opposite side of the channel region than the first source/drain region, wherein the second source/drain region is a metal region. A pocket region of a second conductivity type opposite the first conductivity type is horizontally between the channel region and the second source/drain region.

摘要翻译： 半导体器件包括沟道区; 沟道区上的栅极电介质; 以及在栅极电介质上的栅电极。 第一源极/漏极区域与栅极电介质相邻，其中第一源极/漏极区域是半导体区域并且具有第一导电类型。 第二源极/漏极区域在沟道区域的与第一源极/漏极区域相反的一侧上，其中第二源极/漏极区域是金属区域。 与第一导电类型相反的第二导电类型的口袋区域在沟道区域和第二源极/漏极区域之间是水平的。

公开(公告)号：US07429769B2

公开(公告)日：2008-09-30

申请号：US11255389

申请日：2005-10-21

申请人： Carlos H. Diaz ,  Yi-Ming Sheu ,  Syun-Ming Jang ,  Hun-Jan Tao ,  Fu-Liang Yang

发明人： Carlos H. Diaz ,  Yi-Ming Sheu ,  Syun-Ming Jang ,  Hun-Jan Tao ,  Fu-Liang Yang

IPC分类号： H01L29/78

CPC分类号： H01L29/66772 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/78621 ,  H01L29/78654

摘要： A method for forming a field effect transistor device employs a self-aligned etching of a semiconductor substrate to form a recessed channel region in conjunction with a pair of raised source/drain regions. The method also provides for forming and thermally annealing the pair of source/drain regions prior to forming a pair of lightly doped extension regions within the field effect transistor device. In accord with the foregoing features, the field effect transistor device is fabricated with enhanced performance.

摘要翻译： 用于形成场效应晶体管器件的方法采用半导体衬底的自对准蚀刻以与一对凸起的源极/漏极区域结合形成凹陷沟道区域。 该方法还提供了在场效应晶体管器件内形成一对轻掺杂的延伸区域之前，对成对的源/漏区进行形成和热退火。 根据上述特征，以增强的性能制造场效应晶体管器件。

公开(公告)号：US06974730B2

公开(公告)日：2005-12-13

申请号：US10739476

申请日：2003-12-17

申请人： Carlos H. Diaz ,  Yi-Ming Sheu ,  Syun-Ming Jang ,  Hun-Jan Tao ,  Fu-Liang Yang

发明人： Carlos H. Diaz ,  Yi-Ming Sheu ,  Syun-Ming Jang ,  Hun-Jan Tao ,  Fu-Liang Yang

IPC分类号： H01L21/336 ,  H01L29/786

CPC分类号： H01L29/66772 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/78621 ,  H01L29/78654

摘要： A method for forming a field effect transistor device employs a self-aligned etching of a semiconductor substrate to form a recessed channel region in conjunction with a pair of raised source/drain regions. The method also provides for forming and thermally annealing the pair of source/drain regions prior to forming a pair of lightly doped extension regions within the field effect transistor device. In accord with the foregoing features, the field effect transistor device is fabricated with enhanced performance.

摘要翻译： 用于形成场效应晶体管器件的方法采用半导体衬底的自对准蚀刻以与一对凸起的源极/漏极区域结合形成凹陷沟道区域。 该方法还提供了在场效应晶体管器件内形成一对轻掺杂的延伸区域之前，对成对的源/漏区进行形成和热退火。 根据上述特征，以增强的性能制造场效应晶体管器件。