公开(公告)号：US07371629B2

公开(公告)日：2008-05-13

申请号：US10314689

申请日：2002-12-09

申请人： Chu-Yun Fu ,  Chi-Hsun Hsieh ,  Yi-Ming Sheu ,  Syun-Ming Jang

发明人： Chu-Yun Fu ,  Chi-Hsun Hsieh ,  Yi-Ming Sheu ,  Syun-Ming Jang

IPC分类号： H01L21/8237

CPC分类号： H01L21/0217 ,  H01L21/02274 ,  H01L21/28247 ,  H01L21/3185 ,  H01L21/823814 ,  H01L21/823835

摘要： A method is provided for improving Idsat in NMOS and PMOS transistors. A silicon nitride etch stop layer is deposited by a PECVD technique on STI and silicide regions and on sidewall spacers during a MOSFET manufacturing scheme. A dielectric layer is formed on the nitride and then contact holes are fabricated through the dielectric layer and nitride layer to silicide regions and are filled with a metal. For NMOS transistors, silane and NH3 flow rates and a 400° C. temperature are critical in improving NMOS short channel Idsat. Hydrogen content in the nitride is increased by higher NH3 and SiH4 flow rates but does not significantly degrade HCE and Vt. With PMOS transistors, deposition temperature is increased to 550° C. to reduce hydrogen content and improve HCE and Vt stability.

摘要翻译： 提供了一种用于改善NMOS和PMOS晶体管中的Idsat的方法。 在MOSFET制造方案中，通过PECVD技术在STI和硅化物区域和侧壁间隔物上沉积氮化硅蚀刻停止层。 在氮化物上形成介电层，然后通过电介质层和氮化物层到硅化物区域制造接触孔，并填充金属。 对于NMOS晶体管，硅烷和NH 3 3流速和400℃的温度对于改善NMOS短沟道Idsat至关重要。 氮化物中的氢含量通过较高的NH 3和SiH 4 O 3流速而增加，但不会显着降低HCE和Vt。使用PMOS晶体管，沉积温度增加到550° C.降低氢含量，提高HCE和Vt稳定性。

公开(公告)号：US07429769B2

公开(公告)日：2008-09-30

申请号：US11255389

申请日：2005-10-21

申请人： Carlos H. Diaz ,  Yi-Ming Sheu ,  Syun-Ming Jang ,  Hun-Jan Tao ,  Fu-Liang Yang

发明人： Carlos H. Diaz ,  Yi-Ming Sheu ,  Syun-Ming Jang ,  Hun-Jan Tao ,  Fu-Liang Yang

IPC分类号： H01L29/78

CPC分类号： H01L29/66772 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/78621 ,  H01L29/78654

摘要： A method for forming a field effect transistor device employs a self-aligned etching of a semiconductor substrate to form a recessed channel region in conjunction with a pair of raised source/drain regions. The method also provides for forming and thermally annealing the pair of source/drain regions prior to forming a pair of lightly doped extension regions within the field effect transistor device. In accord with the foregoing features, the field effect transistor device is fabricated with enhanced performance.

摘要翻译： 用于形成场效应晶体管器件的方法采用半导体衬底的自对准蚀刻以与一对凸起的源极/漏极区域结合形成凹陷沟道区域。 该方法还提供了在场效应晶体管器件内形成一对轻掺杂的延伸区域之前，对成对的源/漏区进行形成和热退火。 根据上述特征，以增强的性能制造场效应晶体管器件。

公开(公告)号：US06974730B2

公开(公告)日：2005-12-13

申请号：US10739476

申请日：2003-12-17

申请人： Carlos H. Diaz ,  Yi-Ming Sheu ,  Syun-Ming Jang ,  Hun-Jan Tao ,  Fu-Liang Yang

发明人： Carlos H. Diaz ,  Yi-Ming Sheu ,  Syun-Ming Jang ,  Hun-Jan Tao ,  Fu-Liang Yang

IPC分类号： H01L21/336 ,  H01L29/786

CPC分类号： H01L29/66772 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/78621 ,  H01L29/78654

摘要： A method for forming a field effect transistor device employs a self-aligned etching of a semiconductor substrate to form a recessed channel region in conjunction with a pair of raised source/drain regions. The method also provides for forming and thermally annealing the pair of source/drain regions prior to forming a pair of lightly doped extension regions within the field effect transistor device. In accord with the foregoing features, the field effect transistor device is fabricated with enhanced performance.

摘要翻译： 用于形成场效应晶体管器件的方法采用半导体衬底的自对准蚀刻以与一对凸起的源极/漏极区域结合形成凹陷沟道区域。 该方法还提供了在场效应晶体管器件内形成一对轻掺杂的延伸区域之前，对成对的源/漏区进行形成和热退火。 根据上述特征，以增强的性能制造场效应晶体管器件。

公开(公告)号：US20050133830A1

公开(公告)日：2005-06-23

申请号：US10739476

申请日：2003-12-17

申请人： Carlos Diaz ,  Yi-Ming Sheu ,  Syun-Ming Jang ,  Hun-Jan Tao ,  Fu-Liang Yang

发明人： Carlos Diaz ,  Yi-Ming Sheu ,  Syun-Ming Jang ,  Hun-Jan Tao ,  Fu-Liang Yang

IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L21/8234 ,  H01L29/76 ,  H01L31/113

CPC分类号： H01L29/66772 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/78621 ,  H01L29/78654

摘要： A method for forming a field effect transistor device employs a self-aligned etching of a semiconductor substrate to form a recessed channel region in conjunction with a pair of raised source/drain regions. The method also provides for forming and thermally annealing the pair of source/drain regions prior to forming a pair of lightly doped extension regions within the field effect transistor device. In accord with the foregoing features, the field effect transistor device is fabricated with enhanced performance.

摘要翻译： 用于形成场效应晶体管器件的方法采用半导体衬底的自对准蚀刻以与一对凸起的源极/漏极区域结合形成凹陷沟道区域。 该方法还提供了在场效应晶体管器件内形成一对轻掺杂的延伸区域之前，对成对的源/漏区进行形成和热退火。 根据上述特征，以增强的性能制造场效应晶体管器件。

公开(公告)号：US20060033158A1

公开(公告)日：2006-02-16

申请号：US11255389

申请日：2005-10-21

申请人： Carlos Diaz ,  Yi-Ming Sheu ,  Syun-Ming Jang ,  Hun-Jan Tao ,  Fu-Liang Yang

发明人： Carlos Diaz ,  Yi-Ming Sheu ,  Syun-Ming Jang ,  Hun-Jan Tao ,  Fu-Liang Yang

IPC分类号： H01L29/78

CPC分类号： H01L29/66772 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/78621 ,  H01L29/78654

摘要： A method for forming a field effect transistor device employs a self-aligned etching of a semiconductor substrate to form a recessed channel region in conjunction with a pair of raised source/drain regions. The method also provides for forming and thermally annealing the pair of source/drain regions prior to forming a pair of lightly doped extension regions within the field effect transistor device. In accord with the foregoing features, the field effect transistor device is fabricated with enhanced performance.

摘要翻译： 用于形成场效应晶体管器件的方法采用半导体衬底的自对准蚀刻以与一对凸起的源极/漏极区域结合形成凹陷沟道区域。 该方法还提供了在场效应晶体管器件内形成一对轻掺杂的延伸区域之前，对成对的源/漏区进行形成和热退火。 根据上述特征，以增强的性能制造场效应晶体管器件。

公开(公告)号：US06479385B1

公开(公告)日：2002-11-12

申请号：US09583397

申请日：2000-05-31

申请人： Syun-Ming Jang ,  Chu-Yun Fu

发明人： Syun-Ming Jang ,  Chu-Yun Fu

IPC分类号： H01L21302

CPC分类号： H01L21/02238 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/31612 ,  H01L21/31625 ,  H01L21/76801 ,  H01L21/76837

摘要： A process for forming a composite, interlevel dielectric, (ILD), layer, for MOSFET devices, has been developed. The composite ILD layer is comprised with an underlying, undoped silicon glass layer, providing the material needed to fill the narrow spaces between polysilicon gate structures of the MOSFET devices. A P2O5 doped, insulator layer, is next formed on the underlying, undoped silicon glass layer, to provide a mobile ion gettering property. An overlying, undoped silicon glass layer is then deposited and subjected to a chemical mechanical polishing procedure, resulting in the desired planar top surface topography, for the composite ILD layer.

摘要翻译： 已经开发了用于形成MOSFET器件的复合层间电介质（ILD）层的工艺。 复合ILD层包含底层的未掺杂的硅玻璃层，提供填充MOSFET器件的多晶硅栅极结构之间的狭窄空间所需的材料。 随后在下面未掺杂的硅玻璃层上形成P2O5掺杂的绝缘体层，以提供移动离子吸杂性质。 然后沉积覆盖的未掺杂的硅玻璃层，并进行化学机械抛光程序，得到复合ILD层所需的平面顶表面形貌。

公开(公告)号：US06316348B1

公开(公告)日：2001-11-13

申请号：US09838627

申请日：2001-04-20

申请人： Chu Yun Fu ,  Chia Shiung Tsai ,  Syun-Ming Jang

发明人： Chu Yun Fu ,  Chia Shiung Tsai ,  Syun-Ming Jang

IPC分类号： H01L214763

CPC分类号： H01L21/76829 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/76801 ,  H01L21/7681 ,  H01L21/76813

摘要： The present invention provides an anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer and two compatible oxide etch processes. The Si-Rich Silicon oxynitride (SiON) etch barrier layer can be used as a hard mask in a dual damascene structure and as a hard mask for over a polysilicone gate. The invention has the following key elements: 1) Si rich Silicon oxynitride (SiON) ARC layer, 2) Special Silicon oxide Etch process that has a high selectivity of Si-Rich SiON to silicon oxide or SiN; 3) Special Si Rich SiON spacer process for a self aligned contact (SAC). A dual damascene structure is formed by depositing a first dielectric layer. A novel anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer is deposited on top of the first dielectric layer. A first opening is etched in the first insulating layer. A second dielectric layer is deposited on the anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer. A second dual damascene opening is etched into the dielectric layers. The anti-reflective Si-Rich Silicon oxynnitride (SiON) etch barrier layer can also serve as an ARC layer during these operations to reduce the amount of reflectance from conductive region to reduce distortion of the photoresist pattern.

摘要翻译： 本发明提供了抗反射富Si硅氮化硅（SiON）蚀刻阻挡层和两种相容的氧化物蚀刻工艺。 Si富氧硅氮化物（SiON）蚀刻阻挡层可用作双镶嵌结构中的硬掩模，并且可用作多晶硅栅极上的硬掩模。 本发明具有以下关键要素：1）富硅氧氮化硅（SiON）ARC层，2）具有Si富Si硅对硅氧化物或SiN的高选择性的特殊氧化硅蚀刻工艺; 3）用于自对准接触（SAC）的特殊Si Rich SiON隔离工艺。通过沉积第一介电层形成双镶嵌结构。 在第一介电层的顶部沉积有新的抗反射硅富氮硅氮化硅（SiON）蚀刻阻挡层。 在第一绝缘层中蚀刻第一开口。 第二电介质层沉积在抗反射富Si硅氮化硅（SiON）蚀刻阻挡层上。 第二个双镶嵌开口被蚀刻到电介质层中。 在这些操作期间，抗反射Si富硅氧氮化物（SiON）蚀刻阻挡层也可以用作ARC层，以减少来自导电区域的反射率，以减少光致抗蚀剂图案的变形。

公开(公告)号：US06245682B1

公开(公告)日：2001-06-12

申请号：US09266374

申请日：1999-03-11

申请人： Chu-Yun Fu ,  Syun-Ming Jang

发明人： Chu-Yun Fu ,  Syun-Ming Jang

IPC分类号： H01L21311

CPC分类号： H01L21/32139 ,  H01L21/28123 ,  H01L21/31111 ,  H01L21/3145 ,  Y10S438/952

摘要： This invention relates to the fabrication of integrated circuit devices and more particularly to a method for forming and then later removing a silicon oxynitride, SiON, anti-reflection coating (ARC) over a semiconductor substrate, for the purpose of enhancing the resolution of photolithographically defined sub-micron polysilicon gates. The problem addressed by this invention is that the SiON ARC must first be used to reduce optical reflection from a blanket polysilicon surface, during the photolithography exposure step that defines the sub-micron polysilicon gate features, and then the ARC must be removed by a wet etch process that will not chemically attack the gate oxide under the polysilicon gate features or any exposed polysilicon surfaces. This is accomplished with a fabrication method that uses hot phosphoric acid (H3PO4) to preferentially etch the SiON ARC, relative to the thermal gate oxide, while also using thin thermal oxide layers to protect the polysilicon gate surfaces from being severely attacked by the hot H3PO4. This new method also features the ability to tailor the combination of the composition and thickness of the SiON layer and the thickness of the underlying protective thin thermal oxide layer, in order to minimize the undesired high optical reflectivity of the underlying polysilicon surface.

摘要翻译： 本发明涉及集成电路器件的制造，更具体地说，涉及一种用于在半导体衬底上形成并随后去除氧氮化硅SiON，抗反射涂层（ARC）的方法，用于增强光刻定义的分辨率 亚微米多晶硅门。 本发明解决的问题是，在限定亚微米多晶硅栅极特征的光刻曝光步骤期间，必须首先使用SiON ARC来减少来自覆盖多晶硅表面的光学反射，然后必须通过湿法去除ARC 不会在多晶硅栅极特征或任何暴露的多晶硅表面下化学侵蚀栅极氧化物的蚀刻工艺。 这是通过使用热磷酸（H 3 PO 4）相对于热栅氧化物优先蚀刻SiON ARC的制造方法实现的，同时还使用薄的热氧化物层来保护多晶硅栅极表面免受热H3PO4的严重攻击 。 这种新方法还具有能够定制SiON层的组成和厚度以及下面的保护性薄热氧化物层的厚度的组合，以便使底层多晶硅表面的不期望的高光学反射率最小化。

公开(公告)号：US06245669B1

公开(公告)日：2001-06-12

申请号：US09245564

申请日：1999-02-05

申请人： Chu Yun Fu ,  Chia Shiung Tsai ,  Syun-Ming Jang

发明人： Chu Yun Fu ,  Chia Shiung Tsai ,  Syun-Ming Jang

IPC分类号： H01L214763

CPC分类号： H01L21/76829 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/76801 ,  H01L21/7681 ,  H01L21/76813

摘要： The present invention provides an anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer and two compatible oxide etch processes. The Si-Rich Silicon oxynitride (SiON) etch barrier layer can be used as a hard mask in a dual damascene structure and as a hard mask for over a polysilicon gate. The invention has the following key elements: 1) Si rich Silicon oxynitride (SiON) ARC layer, 2) Special Silicon oxide Etch process that has a high selectivity of Si-Rich SiON to silicon oxide or SiN; 3) Special Si Rich SiON spacer process for a self aligned contact (SAC). A dual damascene structure is formed by depositing a first dielectric layer. A novel anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer is deposited on top of the first dielectric layer. A first opening is etched in the first insulating layer. A second dielectric layer is deposited on the anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer. A second dual damascene opening is etched into the dielectric layers. The anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer can also serve as an ARC layer during these operations to reduce the amount of reflectance from conductive region to reduce distortion of the photoresist pattern.

摘要翻译： 本发明提供了抗反射富Si硅氮化硅（SiON）蚀刻阻挡层和两种相容的氧化物蚀刻工艺。 Si富氧硅氮化物（SiON）蚀刻阻挡层可用作双镶嵌结构中的硬掩模，并可用作多晶硅栅极上的硬掩模。 本发明具有以下关键要素：1）富硅氧氮化硅（SiON）ARC层，2）具有Si富Si硅对硅氧化物或SiN的高选择性的特殊氧化硅蚀刻工艺; 3）用于自对准接触（SAC）的特殊Si Rich SiON隔离工艺。通过沉积第一介电层形成双镶嵌结构。 在第一介电层的顶部沉积有新的抗反射硅富氮硅氮化硅（SiON）蚀刻阻挡层。 在第一绝缘层中蚀刻第一开口。 第二电介质层沉积在抗反射富Si硅氮化硅（SiON）蚀刻阻挡层上。 第二个双镶嵌开口被蚀刻到电介质层中。 在这些操作期间，抗反射硅富氮硅氮化物（SiON）蚀刻阻挡层也可以用作ARC层，以减少来自导电区域的反射率，以减少光致抗蚀剂图案的失真。

公开(公告)号：US06207483B1

公开(公告)日：2001-03-27

申请号：US09527183

申请日：2000-03-17

申请人： Chu-Yun Fu ,  Chung-Long Chang ,  Syun-Ming Jang ,  Shwangming Jeng

发明人： Chu-Yun Fu ,  Chung-Long Chang ,  Syun-Ming Jang ,  Shwangming Jeng

IPC分类号： H01L218238

CPC分类号： H01L21/823828 ,  H01L21/28035 ,  H01L21/32115

摘要： There is provided a method for smoothing the surface of undoped polysilicon regions of a CMOS structure, primarily gate regions. A direct HPD-CVD argon sputter is used improve the surface roughness by a factor of more than 50%. The argon plasma sputter may be used either alone or in conjunction with a thin capping layer of oxide, nitride or oxynitride. The devices manufactured using the process exhibit excellent electrical characteristics and improved reliability compared to devices made using conventional manufacturing processes.

摘要翻译： 提供了一种用于平滑CMOS结构的未掺杂多晶硅区域的表面的方法，主要是栅极区域。 使用直接HPD-CVD氩溅射将表面粗糙度提高了50％以上。 氩等离子体溅射可以单独使用或与氧化物，氮化物或氮氧化物的薄覆盖层结合使用。 与使用常规制造工艺制造的器件相比，使用该工艺制造的器件表现出优异的电气特性和改进的可靠性。