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    Unitary interconnection structures integral with a dielectric layer and fabrication methods thereof
    22.
    发明授权
    Unitary interconnection structures integral with a dielectric layer and fabrication methods thereof 有权
    与介电层一体化的单一互连结构及其制造方法

    公开(公告)号：US07312144B2

    公开(公告)日：2007-12-25

    申请号：US10932416

    申请日：2004-09-02

    申请人： Won-Seok Cho ,  Soon-Moon Jung ,  Sung-Bong Kim ,  Hyung-Shin Kwon

    发明人： Won-Seok Cho ,  Soon-Moon Jung ,  Sung-Bong Kim ,  Hyung-Shin Kwon

    IPC分类号： H01L21/4763

    CPC分类号： H01L27/11 ,  G11C11/412 ,  H01L21/76802 ,  H01L21/76895 ,  H01L27/1104

    摘要： An interconnection structure is provided by forming a first damascene interconnect structure that directly connects a first active area in a substrate, a first conductive line on the substrate and/or a first electrode on the substrate with a second active area in the substrate, a second conductive line on the substrate and/or a second electrode on the substrate. A second damascene interconnect structure may directly connect the first active area, the first conductive line and/or the first electrode to the second active area, the second conductive line and/or the second electrode. The first active area, the first conductive line and/or the first electrode connected to the second active area, the second conductive line and/or the second electrode by the first damascene interconnect structure may be different from the first active area, the first conductive line and/or the first electrode and the second active area, the second conductive line and/or the second electrode connected by the second damascene interconnect structure.

    摘要翻译： 通过形成第一镶嵌互连结构来提供互连结构，所述第一镶嵌互连结构直接连接衬底中的第一有源区，衬底上的第一导电线和/或衬底上的第一电极，在衬底中具有第二有源区， 导电线和/或基板上的第二电极。 第二镶嵌互连结构可以将第一有源区，第一导线和/或第一电极直接连接到第二有源区，第二导线和/或第二电极。 第一有源区域，第一导电线路和/或连接到第二有源区域的第一电极，第一导电线路和/或第二电极通过第一镶嵌互连结构可以不同于第一有源区域，第一导电 线路和/或第一电极和第二有源区域，第二导电线路和/或第二电极通过第二镶嵌互连结构连接。

    Method of forming single crystal semiconductor thin film on insulator and semiconductor device fabricated thereby
    23.
    发明申请
    Method of forming single crystal semiconductor thin film on insulator and semiconductor device fabricated thereby 有权
    在绝缘体上形成单晶半导体薄膜的方法和由此制造的半导体器件

    公开(公告)号：US20060097319A1

    公开(公告)日：2006-05-11

    申请号：US11197836

    申请日：2005-08-05

    申请人： Jong-Hyuk Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Kun-Ho Kwak ,  Sung-Jin Kim ,  Jae-Joo Shim

    发明人： Jong-Hyuk Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Kun-Ho Kwak ,  Sung-Jin Kim ,  Jae-Joo Shim

    IPC分类号： H01L27/01

    CPC分类号： H01L21/8221 ,  H01L21/28525 ,  H01L21/76877 ,  H01L27/0688 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/12 ,  H01L29/785

    摘要： Methods of forming a single crystal semiconductor thin film on an insulator and semiconductor devices fabricated thereby are provided. The methods include forming an interlayer insulating layer on a single crystal semiconductor layer. A single crystal semiconductor plug is formed to penetrate the interlayer insulating layer. A semiconductor oxide layer is formed within the single crystal semiconductor plug using an ion implantation technique and an annealing technique. As a result, the single crystal semiconductor plug is divided into a lower plug and an upper single crystal semiconductor plug with the semiconductor oxide layer being interposed therebetween. That is, the upper single crystal semiconductor plug is electrically insulated from the lower plug by the semiconductor oxide layer. A single crystal semiconductor pattern is formed to be in contact with the upper single crystal semiconductor plug and cover the interlayer insulating layer. The single crystal semiconductor pattern is grown by an epitaxy growth technique using the upper single crystal semiconductor plug as a seed layer, or by a solid epitaxy growth technique using the upper single crystal semiconductor plug as a seed layer.

    摘要翻译： 提供了在绝缘体上形成单晶半导体薄膜的方法和由此制造的半导体器件。 所述方法包括在单晶半导体层上形成层间绝缘层。 形成单晶半导体插塞以穿透层间绝缘层。 使用离子注入技术和退火技术在单晶半导体插头内形成半导体氧化物层。 结果，单晶半导体插头被分成下插头和上部单晶半导体插头，半导体氧化物层之间插入其中。 也就是说，上单晶半导体插头通过半导体氧化物层与下插塞电绝缘。 单晶半导体图案形成为与上单晶半导体插头接触并覆盖层间绝缘层。 通过使用上部单晶半导体插塞作为种子层的外延生长技术，或通过使用上部单晶半导体插塞作为种子层的固体外延生长技术，生长单晶半导体图案。

    Unitary interconnection structures integral with a dielectric layer
    24.
    发明授权
    Unitary interconnection structures integral with a dielectric layer 有权
    与介电层成一体的单一互连结构

    公开(公告)号：US06806180B2

    公开(公告)日：2004-10-19

    申请号：US10426266

    申请日：2003-04-30

    申请人： Won-Seok Cho ,  Soon-Moon Jung ,  Sung-Bong Kim ,  Hyung-Shin Kwon

    发明人： Won-Seok Cho ,  Soon-Moon Jung ,  Sung-Bong Kim ,  Hyung-Shin Kwon

    IPC分类号： H01L214763

    CPC分类号： H01L27/11 ,  G11C11/412 ,  H01L21/76802 ,  H01L21/76895 ,  H01L27/1104

    摘要： An interconnection structure is provided by foiling a first damascene interconnect structure that directly connects a first active area in a substrate, a first conductive line on the substrate and/or a first electrode on the substrate with a second active area in the substrate, a second conductive line on the substrate and/or a second electrode on the substrate. A second damascene interconnect structure may directly connect the first active area, the first conductive line and/or the first electrode to the second active area, the second conductive line and/or the second electrode. The first active area, the first conductive line and/or the first electrode connected to the second active area, the second conductive line and/or the second electrode by the first damascene interconnect structure may be different from the first active area, the first conductive line and/or the first electrode and the second active area, the second conductive line and/or the second electrode connected by the second damascene interconnect structure.

    摘要翻译： 通过形成第一镶嵌互连结构来提供互连结构，所述第一镶嵌互连结构直接连接衬底中的第一有源区，衬底上的第一导电线和/或衬底上的第一电极，在衬底中具有第二有源区，第二 导电线和/或基板上的第二电极。 第二镶嵌互连结构可以将第一有源区，第一导线和/或第一电极直接连接到第二有源区，第二导线和/或第二电极。 第一有源区域，第一导电线路和/或连接到第二有源区域的第一电极，第一导电线路和/或第二电极通过第一镶嵌互连结构可以不同于第一有源区域，第一导电 线路和/或第一电极和第二有源区域，第二导电线路和/或第二电极通过第二镶嵌互连结构连接。

    Body-tied-to-source MOSFETs with asymmetrical source and drain regions and methods of fabricating the same
    28.
    发明申请
    Body-tied-to-source MOSFETs with asymmetrical source and drain regions and methods of fabricating the same 有权
    具有不对称源极和漏极区域的体耦对源MOSFET及其制造方法

    公开(公告)号：US20060049467A1

    公开(公告)日：2006-03-09

    申请号：US11179236

    申请日：2005-07-12

    申请人： Hoon Lim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hun Jeong

    发明人： Hoon Lim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hun Jeong

    IPC分类号： H01L27/01

    CPC分类号： H01L29/0847 ,  H01L21/743 ,  H01L27/11 ,  H01L27/1108 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66772 ,  H01L29/7834 ,  H01L29/78612 ,  H01L29/78654

    摘要： A metal oxide semiconductor field effect transistor (MOSFET) includes a body pattern of a first conductivity type disposed on an insulating layer. A gate electrode is disposed on the body pattern. A drain region of a second conductivity type is disposed on the insulating layer and having a sidewall in contact with a first sidewall of the body pattern. An impurity-doped region of the first conductivity type is disposed on the insulating layer and having a sidewall in contact with a second sidewall of the body pattern. The MOSFET further includes a source region of the second conductivity type disposed on the impurity-doped region and having a sidewall in contact with the second sidewall of the body pattern, and a contact plug extending through the source region to contact the impurity-doped region.

    摘要翻译： 金属氧化物半导体场效应晶体管（MOSFET）包括设置在绝缘层上的第一导电类型的主体图案。 栅电极设置在主体图案上。 第二导电类型的漏极区域设置在绝缘层上并且具有与主体图案的第一侧壁接触的侧壁。 第一导电类型的杂质掺杂区域设置在绝缘层上并且具有与主体图案的第二侧壁接触的侧壁。 MOSFET还包括设置在杂质掺杂区域上并具有与主体图案的第二侧壁接触的侧壁的第二导电类型的源极区域，以及延伸穿过源极区域以接触杂质掺杂区域的接触插塞 。

    Semiconductor devices with a source/drain formed on a recessed portion of an isolation layer and methods of fabricating the same
    29.
    发明申请
    Semiconductor devices with a source/drain formed on a recessed portion of an isolation layer and methods of fabricating the same 有权
    在隔离层的凹部形成有源极/漏极的半导体器件及其制造方法

    公开(公告)号：US20050106838A1

    公开(公告)日：2005-05-19

    申请号：US10967374

    申请日：2004-10-18

    申请人： Hoon Lim ,  Soon-Moon Jung ,  Won-Seok Cho

    发明人： Hoon Lim ,  Soon-Moon Jung ,  Won-Seok Cho

    IPC分类号： H01L21/335 ,  H01L21/8234 ,  H01L21/336 ,  H01L21/76

    CPC分类号： H01L21/823481 ,  H01L21/823418

    摘要： Semiconductor devices and methods of fabricating semiconductor devices that include a substrate and a device isolation layer in the substrate that defines an active region of the substrate are provided. The device isolation layer has a vertically protruding portion having a sidewall that extends vertically beyond a surface of the substrate. An epitaxial layer is provided on the surface of the substrate in the active region and extends onto the device isolation layer. The epitaxial layer is spaced apart from the sidewall of the vertically protruding portion of the device isolation layer. A gate pattern is provided on the epitaxial layer and source/drain regions are provided in the epitaxial layer at opposite sides of the gate pattern.

    摘要翻译： 提供制造半导体器件的半导体器件和方法，其包括限定衬底的有源区的衬底中的衬底和器件隔离层。 器件隔离层具有垂直突出部分，其具有垂直延伸超出衬底表面的侧壁。 在有源区中的衬底的表面上提供外延层并延伸到器件隔离层上。 外延层与器件隔离层的垂直突出部分的侧壁间隔开。 在外延层上提供栅极图案，并且在栅极图案的相对侧的外延层中设置源极/漏极区域。

    Unitary interconnection structures integral with a dielectric layer and fabrication methods thereof
    30.
    发明申请
    Unitary interconnection structures integral with a dielectric layer and fabrication methods thereof 有权
    与介电层一体化的单一互连结构及其制造方法

    公开(公告)号：US20050029664A1

    公开(公告)日：2005-02-10

    申请号：US10932416

    申请日：2004-09-02

    申请人： Won-Seok Cho ,  Soon-Moon Jung ,  Sung-Bong Kim ,  Hyung-Shin Kwon

    发明人： Won-Seok Cho ,  Soon-Moon Jung ,  Sung-Bong Kim ,  Hyung-Shin Kwon

    IPC分类号： G11C11/412 ,  H01L21/768 ,  H01L21/8244 ,  H01L27/11 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L27/11 ,  G11C11/412 ,  H01L21/76802 ,  H01L21/76895 ,  H01L27/1104

    摘要： An interconnection structure is provided by forming a first damascene interconnect structure that directly connects a first active area in a substrate, a first conductive line on the substrate and/or a first electrode on the substrate with a second active area in the substrate, a second conductive line on the substrate and/or a second electrode on the substrate. A second damascene interconnect structure may directly connect the first active area, the first conductive line and/or the first electrode to the second active area, the second conductive line and/or the second electrode. The first active area, the first conductive line and/or the first electrode connected to the second active area, the second conductive line and/or the second electrode by the first damascene interconnect structure may be different from the first active area, the first conductive line and/or the first electrode and the second active area, the second conductive line and/or the second electrode connected by the second damascene interconnect structure.

    摘要翻译： 通过形成第一镶嵌互连结构来提供互连结构，所述第一镶嵌互连结构直接连接衬底中的第一有源区，衬底上的第一导电线和/或衬底上的第一电极，在衬底中具有第二有源区， 导电线和/或基板上的第二电极。 第二镶嵌互连结构可以将第一有源区，第一导线和/或第一电极直接连接到第二有源区，第二导线和/或第二电极。 第一有源区域，第一导电线路和/或连接到第二有源区域的第一电极，第一导电线路和/或第二电极通过第一镶嵌互连结构可以不同于第一有源区域，第一导电 线路和/或第一电极和第二有源区域，第二导电线路和/或第二电极通过第二镶嵌互连结构连接。