公开(公告)号：US20080217734A1

公开(公告)日：2008-09-11

申请号：US11715631

申请日：2007-03-08

Applicant: Yung-Lung Lin ,  Jui-Jen Wu ,  Shine Chung ,  Fu-Lung Hsuen

Inventor： Yung-Lung Lin ,  Jui-Jen Wu ,  Shine Chung ,  Fu-Lung Hsuen

IPC: H01L29/00

CPC classification number: G11C11/5692 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A multi-level electrical fuse system comprises at least one fuse box having at least one electrical fuse, a programming device serially coupled to the electrical fuse, and a variable power supply coupled to the fuse box and configured to generate two or more voltage levels.

Abstract translation: 多级电熔丝系统包括至少一个具有至少一个电熔丝的保险丝盒，串联耦合到电熔丝的编程装置，以及耦合到保险丝盒并被配置成产生两个或多个电压电平的可变电源。

公开(公告)号：US20080112212A1

公开(公告)日：2008-05-15

申请号：US11598385

申请日：2006-11-13

Applicant: Dao-Ping Wang ,  Hung-Jen Liao ,  Kun Lung Chen ,  Yung-Lung Lin ,  Jun-Jen Wu ,  Chen Yen-Huei

Inventor： Dao-Ping Wang ,  Hung-Jen Liao ,  Kun Lung Chen ,  Yung-Lung Lin ,  Jun-Jen Wu ,  Chen Yen-Huei

IPC: G11C11/00

CPC classification number: G11C11/412 ,  G11C8/08 ,  G11C11/413 ,  G11C11/418

Abstract: A system and method for writing a SRAM cell coupled to complimentary first and second bit-lines (BLs) is disclosed, the method comprising asserting a word-line (WL) selecting the SRAM cell to a first positive voltage, providing a second positive voltage at the first BL, providing a first negative voltage at the second BL, and asserting a plurality of WLs not selecting the SRAM cell to a second negative voltage, wherein the writing margin of the SRAM cell is increased.

Abstract translation: 公开了一种用于写入耦合到互补的第一和第二位线（BL）的SRAM单元的系统和方法，所述方法包括断言将SRAM单元选择为第一正电压的字线（WL），提供第二正电压 在第一BL处，在第二BL处提供第一负电压，并且将不选择SRAM单元的多个WL确定为第二负电压，其中增加了SRAM单元的写入裕度。

公开(公告)号：US07271644B2

公开(公告)日：2007-09-18

申请号：US11328780

申请日：2006-01-10

Applicant: Yung-Lung Lin ,  Jui-Jen Wu ,  Hung-Jen Liao

Inventor： Yung-Lung Lin ,  Jui-Jen Wu ,  Hung-Jen Liao

IPC: H01H37/76 ,  H01H85/00

CPC classification number: G11C11/56 ,  G11C17/18

Abstract: An integrated circuit for programming an electrical fuse includes a first programming device coupled to the electrical fuse for selectively providing the same with a first programming current, and a second programming device coupled to the electrical fuse for selectively providing the same with a second programming current. A detection module is coupled to the electrical fuse for generating an output indicating a resistance level of the electrical fuse, wherein the resistance level has three or more predetermined states, which are provided by selectively programming the electrical fuse with the first or second programming current.

Abstract translation: 用于编程电熔丝的集成电路包括耦合到电熔丝的第一编程装置，用于选择性地为其提供第一编程电流;以及耦合到电熔丝的第二编程装置，用于选择性地将其提供给第二编程电流。 检测模块耦合到电熔丝，用于产生指示电熔丝的电阻电平的输出，其中电阻电平具有三个或更多个预定状态，这些状态通过用第一或第二编程电流选择性地编程电熔丝来提供。

公开(公告)号：US08223575B2

公开(公告)日：2012-07-17

申请号：US11715631

申请日：2007-03-08

Applicant: Yung-Lung Lin ,  Jui-Jen Wu ,  Shine Chung ,  Fu-Lung Hsuen

Inventor： Yung-Lung Lin ,  Jui-Jen Wu ,  Shine Chung ,  Fu-Lung Hsuen

IPC: G11C17/18 ,  G11C17/14 ,  G11C17/16 ,  G11C17/00

CPC classification number: G11C11/5692 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A multi-level electrical fuse system comprises at least one fuse box having at least one electrical fuse, a programming device serially coupled to the electrical fuse, and a variable power supply coupled to the fuse box and configured to generate two or more voltage levels.

Abstract translation: 多级电熔丝系统包括至少一个具有至少一个电熔丝的保险丝盒，串联耦合到电熔丝的编程装置，以及耦合到保险丝盒并被配置为产生两个或多个电压电平的可变电源。

公开(公告)号：US07535788B2

公开(公告)日：2009-05-19

申请号：US11636173

申请日：2006-12-08

Applicant: Jui-Jen Wu ,  Kun-Lung Chen ,  Hung-Jen Liao ,  Yung-Lung Lin ,  Chen Yen-Huei ,  Dao-Ping Wang

Inventor： Jui-Jen Wu ,  Kun-Lung Chen ,  Hung-Jen Liao ,  Yung-Lung Lin ,  Chen Yen-Huei ,  Dao-Ping Wang

IPC: G11C5/14

CPC classification number: G11C11/413

Abstract: A writing dynamic power control circuit is disclosed, which comprises a BL and its complementary BLB, at least one memory cell coupled to both the BL and BLB, a first NMOS transistor having a source, a drain and a gate coupled to the BL, the Vss and a first data signal, respectively, a second NMOS transistor having a source, a drain and a gate coupled to the BLB, the Vss and a second data signal, respectively, wherein the second data signal is complementary to the first data signal, a first PMOS transistor having a source, a drain and a gate coupled to a high voltage power supply (CVDD) node, the BLB and the BL, respectively, and a second PMOS transistor having a source, a drain and a gate coupled to the CVDD node, the BL and the BLB, respectively.

Abstract translation: 公开了一种写入动态功率控制电路，其包括BL及其互补BLB，耦合到BL和BLB的至少一个存储单元，具有耦合到BL的源极，漏极和栅极的第一NMOS晶体管， Vss和第一数据信号，分别具有耦合到BLB的源极，漏极和栅极的第二NMOS晶体管，Vss和第二数据信号，其中第二数据信号与第一数据信号互补， 第一PMOS晶体管，具有源极，漏极和栅极，分别耦合到高电压电源（CVDD）节点，BLB和BL，以及第二PMOS晶体管，其具有源极，漏极和栅极耦合到 CVDD节点，BL和BLB。

公开(公告)号：US20090042113A1

公开(公告)日：2009-02-12

申请号：US12040922

申请日：2008-03-03

Applicant: Yong-Mao Lin ,  Wen-Lung Chen ,  Yung-Lung Lin ,  Fu-Chuan Tsai ,  Wei-Ya Wang ,  Chun-Chieh Tsao ,  Shu-Chin Lee

Inventor： Yong-Mao Lin ,  Wen-Lung Chen ,  Yung-Lung Lin ,  Fu-Chuan Tsai ,  Wei-Ya Wang ,  Chun-Chieh Tsao ,  Shu-Chin Lee

IPC: G03F7/16

CPC classification number: G02B5/201

Abstract: A manufacturing method of a filter is provided. The manufacturing method includes steps as follows. First, a substrate is provided and a black matrix is formed on the substrate. The black matrix has a number of openings arranged in array. Next, a filter material is individually formed in the openings by inkjet printing or other methods, and the filter material includes a solvent and a dye mixed with the solvent. Thereafter, a thermal treatment is performed and an evaporation rate of the solvent during the thermal treatment is reduced, so as to cure the filter material. As the evaporation rate of the solvent is relatively slow, the filter material is still flowable during the thermal treatment. Hence, the cured filter material has a flat surface. The filter fabricated by the above manufacturing method has an even hue and a well flattened surface.

Abstract translation: 提供了一种过滤器的制造方法。 制造方法包括以下步骤。 首先，提供基板，并在基板上形成黑矩阵。 黑色矩阵具有排列成阵列的多个开口。 接下来，通过喷墨印刷或其它方法在开口中分别形成过滤材料，过滤材料包括溶剂和与溶剂混合的染料。 此后，进行热处理，并且在热处理期间溶剂的蒸发速率降低，以使过滤材料固化。 当溶剂的蒸发速率相对较慢时，过滤材料在热处理期间仍然是可流动的。 因此，固化的过滤材料具有平坦的表面。 通过上述制造方法制造的过滤器具有均匀色调和平坦的表面。

公开(公告)号：US20090035518A1

公开(公告)日：2009-02-05

申请号：US11944415

申请日：2007-11-22

Applicant: Wei-Ya Wang ,  Shu-Chin Lee ,  Wen-Lung Chen ,  Fu-Chuan Tsai ,  Yung-Lung Lin ,  Yong-Mao Lin ,  Chun-Chieh Tsao

Inventor： Wei-Ya Wang ,  Shu-Chin Lee ,  Wen-Lung Chen ,  Fu-Chuan Tsai ,  Yung-Lung Lin ,  Yong-Mao Lin ,  Chun-Chieh Tsao

IPC: G03F1/00

CPC classification number: G03F7/0007 ,  G02B5/201 ,  G02B5/223

Abstract: A manufacturing method of a color filter including following steps is provided. First, a partition is formed on a substrate to form a plurality of pixel regions on the substrate. Next, a color pigment is provided along a continuous pigment-providing route, so as to form the color pigment on a sequence of pixel regions among the plurality of pixel regions and the partition. The method mentioned above can prevent the unfilled phenomenon of the pigment around the corners of the pixel region. Besides, a liquid crystal display panel having the color filter is also provided.

Abstract translation: 提供了包括以下步骤的滤色器的制造方法。 首先，在基板上形成分隔，以在基板上形成多个像素区域。 接着，沿着连续的颜料提供路径设置彩色颜料，以便在多个像素区域和分隔物之间的像素区域序列上形成彩色颜料。 上述方法可以防止像素区域的角部附近的颜料的未填充现象。 此外，还提供了具有滤色器的液晶显示面板。

公开(公告)号：US20080144419A1

公开(公告)日：2008-06-19

申请号：US11638187

申请日：2006-12-13

Applicant: Jui-Jen Wu ,  Kun-Lung Chen ,  Hung-Jen Liao ,  Yung-Lung Lin ,  Chen Yen-Huei ,  Dao-Ping Wang

Inventor： Jui-Jen Wu ,  Kun-Lung Chen ,  Hung-Jen Liao ,  Yung-Lung Lin ,  Chen Yen-Huei ,  Dao-Ping Wang

IPC: G11C5/14

CPC classification number: G11C11/412 ,  G11C11/413

Abstract: A power control circuit for an integrated circuit module includes at least one switch device coupled between a supply voltage and a power node of the integrated circuit module; and a switch control module having a first terminal coupled to the switch device, a second terminal coupled to a control signal, a third terminal coupled to a first storage node of at least one tracking cell, a fourth terminal coupled to a second storage node of the tracking cell, and a fifth terminal coupled to the power node of the integrated circuit module, for controlling the switch device to pass the supply voltage to the power node with or without a substantial voltage drop depending on an operation mode of the integrated circuit module.

Abstract translation: 用于集成电路模块的功率控制电路包括耦合在电源电压和集成电路模块的功率节点之间的至少一个开关装置; 以及开关控制模块，其具有耦合到所述开关装置的第一端子，耦合到控制信号的第二端子，耦合到至少一个跟踪单元的第一存储节点的第三端子，耦合到所述至少一个跟踪单元的第二存储节点的第四端子 跟踪单元和耦合到集成电路模块的功率节点的第五端子，用于根据集成电路模块的操作模式控制开关装置将电源电压传递到功率节点，具有或不具有实质的电压降 。

公开(公告)号：US07319355B2

公开(公告)日：2008-01-15

申请号：US11324472

申请日：2006-01-03

Applicant: Jui-Jen Wu ,  Yung-Lung Lin

Inventor： Jui-Jen Wu ,  Yung-Lung Lin

IPC: G06F1/04

CPC classification number: G06F1/04

Abstract: A system for generating a pulse signal in response to a clock signal includes a latch module for generating a latched output in response to a leading edge of the clock signal. A delay module is coupled to the latch module for delaying the latched output. A first logic device having a first input terminal coupled to the latch module and a second input terminal is coupled to the delay module for generating the pulse signal, which has a pulse width determined by a delay time of the latched output passing through the delay module. The pulse signal is coupled to the latch module for resetting the latch module when the pulse signal is not asserted.

Abstract translation: 用于响应于时钟信号产生脉冲信号的系统包括用于响应于时钟信号的前沿产生锁存输出的锁存模块。 延迟模块耦合到锁存模块，用于延迟锁存的输出。 具有耦合到锁存模块的第一输入端和第二输入端的第一逻辑器件被耦合到延迟模块以产生脉冲信号，该脉冲信号具有由通过延迟模块的锁存输出的延迟时间确定的脉冲宽度 。 脉冲信号耦合到锁存模块，用于当脉冲信号未被确认时复位锁存模块。

公开(公告)号：US20070152726A1

公开(公告)日：2007-07-05

申请号：US11324472

申请日：2006-01-03

Applicant: Jui-Jen Wu ,  Yung-Lung Lin

Inventor： Jui-Jen Wu ,  Yung-Lung Lin

IPC: G06F1/04

CPC classification number: G06F1/04

Abstract: A system for generating a pulse signal in response to a clock signal includes a latch module for generating a latched output in response to a leading edge of the clock signal. A delay module is coupled to the latch module for delaying the latched output. A first logic device having a first input terminal coupled to the latch module and a second input terminal is coupled to the delay module for generating the pulse signal, which has a pulse width determined by a delay time of the latched output passing through the delay module. The pulse signal is coupled to the latch module for resetting the latch module when the pulse signal is not asserted.

Abstract translation: 用于响应于时钟信号产生脉冲信号的系统包括用于响应于时钟信号的前沿产生锁存输出的锁存模块。 延迟模块耦合到锁存模块，用于延迟锁存的输出。 具有耦合到锁存模块的第一输入端和第二输入端的第一逻辑器件被耦合到延迟模块以产生脉冲信号，该脉冲信号具有由通过延迟模块的锁存输出的延迟时间确定的脉冲宽度 。 脉冲信号耦合到锁存模块，用于当脉冲信号未被确认时复位锁存模块。