公开(公告)号：US20120243290A1

公开(公告)日：2012-09-27

申请号：US13492635

申请日：2012-06-08

Applicant: Yung-Lung Lin ,  Jui-Jen Wu ,  Shine Chung ,  Fu-Lung Hsueh

Inventor： Yung-Lung Lin ,  Jui-Jen Wu ,  Shine Chung ,  Fu-Lung Hsueh

IPC: G11C17/16

CPC classification number: G11C11/5692 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for programming a multi-level electrical fuse system comprises providing a fuse box with an electrical fuse and providing one of at least two fuse writing voltages to the electrical fuse to program the electrical fuse to one of at least two resistance states. The fuse box comprises at least one electrical fuse, a programming device serially coupled to the electrical fuse, and a variable power supply coupled to the fuse box and configured to generate two or more voltage levels.

Abstract translation: 一种用于编程多电平电熔丝系统的方法包括：提供具有电熔丝的保险丝盒，并向所述电熔丝提供至少两个熔丝写入电压中的一个，以将所述电熔丝编程为至少两个电阻状态之一。 保险丝盒包括至少一个电熔丝，串联耦合到电熔丝的编程装置，以及耦合到保险丝盒并配置成产生两个或多个电压电平的可变电源。

公开(公告)号：US07577052B2

公开(公告)日：2009-08-18

申请号：US11638187

申请日：2006-12-13

Applicant: Jui-Jen Wu ,  Kun-Lung Chen ,  Hung-Jen Liao ,  Yung-Lung Lin ,  Chen Yen-Huei ,  Dao-Ping Wang

Inventor： Jui-Jen Wu ,  Kun-Lung Chen ,  Hung-Jen Liao ,  Yung-Lung Lin ,  Chen Yen-Huei ,  Dao-Ping Wang

IPC: G11C5/10

CPC classification number: G11C11/412 ,  G11C11/413

Abstract: A power control circuit for an integrated circuit module includes at least one switch device coupled between a supply voltage and a power node of the integrated circuit module; and a switch control module having a first terminal coupled to the switch device, a second terminal coupled to a control signal, a third terminal coupled to a first storage node of at least one tracking cell, a fourth terminal coupled to a second storage node of the tracking cell, and a fifth terminal coupled to the power node of the integrated circuit module, for controlling the switch device to pass the supply voltage to the power node with or without a substantial voltage drop depending on an operation mode of the integrated circuit module.

Abstract translation: 用于集成电路模块的功率控制电路包括耦合在电源电压和集成电路模块的功率节点之间的至少一个开关装置; 以及开关控制模块，其具有耦合到所述开关装置的第一端子，耦合到控制信号的第二端子，耦合到至少一个跟踪单元的第一存储节点的第三端子，耦合到所述至少一个跟踪单元的第二存储节点的第四端子 跟踪单元和耦合到集成电路模块的功率节点的第五端子，用于根据集成电路模块的操作模式控制开关装置将电源电压传递到功率节点，具有或不具有实质的电压降 。

公开(公告)号：US20080158939A1

公开(公告)日：2008-07-03

申请号：US11619103

申请日：2007-01-02

Applicant: Yen-Huei Chen ,  Hung-Jen Liao ,  Kun-Lung Chen ,  Jui-Jen Wu ,  Yung-Lung Lin ,  Dao-Ping Wang

Inventor： Yen-Huei Chen ,  Hung-Jen Liao ,  Kun-Lung Chen ,  Jui-Jen Wu ,  Yung-Lung Lin ,  Dao-Ping Wang

IPC: G11C11/00

CPC classification number: G11C11/412 ,  G11C11/413

Abstract: A memory includes a plurality of cells arranged in a matrix having a plurality of rows and a plurality of columns, wherein each cell is capable of storing a bit. Each cell is coupled between a first power supply node that receives a power supply voltage and a second power supply node that receives a second voltage. A plurality of word lines are associated with the memory cells and supplied by a third voltage in read or write operation. The third voltage is a suppressed power supply voltage. The second voltage is negative in read operation and positive in write operation.

Abstract translation: 存储器包括以具有多个行和多个列的矩阵的形式排列的多个单元，其中每个单元能够存储位。 每个单元耦合在接收电源电压的第一电源节点和接收第二电压的第二电源节点之间。 多个字线与存储器单元相关联并且在读或写操作中由第三电压提供。 第三电压是抑制电源电压。 读操作中的第二电压为负，写操作为正。

公开(公告)号：US08223575B2

公开(公告)日：2012-07-17

申请号：US11715631

申请日：2007-03-08

Applicant: Yung-Lung Lin ,  Jui-Jen Wu ,  Shine Chung ,  Fu-Lung Hsuen

Inventor： Yung-Lung Lin ,  Jui-Jen Wu ,  Shine Chung ,  Fu-Lung Hsuen

IPC: G11C17/18 ,  G11C17/14 ,  G11C17/16 ,  G11C17/00

CPC classification number: G11C11/5692 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A multi-level electrical fuse system comprises at least one fuse box having at least one electrical fuse, a programming device serially coupled to the electrical fuse, and a variable power supply coupled to the fuse box and configured to generate two or more voltage levels.

Abstract translation: 多级电熔丝系统包括至少一个具有至少一个电熔丝的保险丝盒，串联耦合到电熔丝的编程装置，以及耦合到保险丝盒并被配置为产生两个或多个电压电平的可变电源。

公开(公告)号：US07535788B2

公开(公告)日：2009-05-19

申请号：US11636173

申请日：2006-12-08

Applicant: Jui-Jen Wu ,  Kun-Lung Chen ,  Hung-Jen Liao ,  Yung-Lung Lin ,  Chen Yen-Huei ,  Dao-Ping Wang

Inventor： Jui-Jen Wu ,  Kun-Lung Chen ,  Hung-Jen Liao ,  Yung-Lung Lin ,  Chen Yen-Huei ,  Dao-Ping Wang

IPC: G11C5/14

CPC classification number: G11C11/413

Abstract: A writing dynamic power control circuit is disclosed, which comprises a BL and its complementary BLB, at least one memory cell coupled to both the BL and BLB, a first NMOS transistor having a source, a drain and a gate coupled to the BL, the Vss and a first data signal, respectively, a second NMOS transistor having a source, a drain and a gate coupled to the BLB, the Vss and a second data signal, respectively, wherein the second data signal is complementary to the first data signal, a first PMOS transistor having a source, a drain and a gate coupled to a high voltage power supply (CVDD) node, the BLB and the BL, respectively, and a second PMOS transistor having a source, a drain and a gate coupled to the CVDD node, the BL and the BLB, respectively.

Abstract translation: 公开了一种写入动态功率控制电路，其包括BL及其互补BLB，耦合到BL和BLB的至少一个存储单元，具有耦合到BL的源极，漏极和栅极的第一NMOS晶体管， Vss和第一数据信号，分别具有耦合到BLB的源极，漏极和栅极的第二NMOS晶体管，Vss和第二数据信号，其中第二数据信号与第一数据信号互补， 第一PMOS晶体管，具有源极，漏极和栅极，分别耦合到高电压电源（CVDD）节点，BLB和BL，以及第二PMOS晶体管，其具有源极，漏极和栅极耦合到 CVDD节点，BL和BLB。

公开(公告)号：US20080144419A1

公开(公告)日：2008-06-19

申请号：US11638187

申请日：2006-12-13

Applicant: Jui-Jen Wu ,  Kun-Lung Chen ,  Hung-Jen Liao ,  Yung-Lung Lin ,  Chen Yen-Huei ,  Dao-Ping Wang

Inventor： Jui-Jen Wu ,  Kun-Lung Chen ,  Hung-Jen Liao ,  Yung-Lung Lin ,  Chen Yen-Huei ,  Dao-Ping Wang

IPC: G11C5/14

CPC classification number: G11C11/412 ,  G11C11/413

Abstract: A power control circuit for an integrated circuit module includes at least one switch device coupled between a supply voltage and a power node of the integrated circuit module; and a switch control module having a first terminal coupled to the switch device, a second terminal coupled to a control signal, a third terminal coupled to a first storage node of at least one tracking cell, a fourth terminal coupled to a second storage node of the tracking cell, and a fifth terminal coupled to the power node of the integrated circuit module, for controlling the switch device to pass the supply voltage to the power node with or without a substantial voltage drop depending on an operation mode of the integrated circuit module.

Abstract translation: 用于集成电路模块的功率控制电路包括耦合在电源电压和集成电路模块的功率节点之间的至少一个开关装置; 以及开关控制模块，其具有耦合到所述开关装置的第一端子，耦合到控制信号的第二端子，耦合到至少一个跟踪单元的第一存储节点的第三端子，耦合到所述至少一个跟踪单元的第二存储节点的第四端子 跟踪单元和耦合到集成电路模块的功率节点的第五端子，用于根据集成电路模块的操作模式控制开关装置将电源电压传递到功率节点，具有或不具有实质的电压降 。

公开(公告)号：US07319355B2

公开(公告)日：2008-01-15

申请号：US11324472

申请日：2006-01-03

Applicant: Jui-Jen Wu ,  Yung-Lung Lin

Inventor： Jui-Jen Wu ,  Yung-Lung Lin

IPC: G06F1/04

CPC classification number: G06F1/04

Abstract: A system for generating a pulse signal in response to a clock signal includes a latch module for generating a latched output in response to a leading edge of the clock signal. A delay module is coupled to the latch module for delaying the latched output. A first logic device having a first input terminal coupled to the latch module and a second input terminal is coupled to the delay module for generating the pulse signal, which has a pulse width determined by a delay time of the latched output passing through the delay module. The pulse signal is coupled to the latch module for resetting the latch module when the pulse signal is not asserted.

Abstract translation: 用于响应于时钟信号产生脉冲信号的系统包括用于响应于时钟信号的前沿产生锁存输出的锁存模块。 延迟模块耦合到锁存模块，用于延迟锁存的输出。 具有耦合到锁存模块的第一输入端和第二输入端的第一逻辑器件被耦合到延迟模块以产生脉冲信号，该脉冲信号具有由通过延迟模块的锁存输出的延迟时间确定的脉冲宽度 。 脉冲信号耦合到锁存模块，用于当脉冲信号未被确认时复位锁存模块。

公开(公告)号：US20070152726A1

公开(公告)日：2007-07-05

申请号：US11324472

申请日：2006-01-03

Applicant: Jui-Jen Wu ,  Yung-Lung Lin

Inventor： Jui-Jen Wu ,  Yung-Lung Lin

IPC: G06F1/04

CPC classification number: G06F1/04

Abstract: A system for generating a pulse signal in response to a clock signal includes a latch module for generating a latched output in response to a leading edge of the clock signal. A delay module is coupled to the latch module for delaying the latched output. A first logic device having a first input terminal coupled to the latch module and a second input terminal is coupled to the delay module for generating the pulse signal, which has a pulse width determined by a delay time of the latched output passing through the delay module. The pulse signal is coupled to the latch module for resetting the latch module when the pulse signal is not asserted.

Abstract translation: 用于响应于时钟信号产生脉冲信号的系统包括用于响应于时钟信号的前沿产生锁存输出的锁存模块。 延迟模块耦合到锁存模块，用于延迟锁存的输出。 具有耦合到锁存模块的第一输入端和第二输入端的第一逻辑器件被耦合到延迟模块以产生脉冲信号，该脉冲信号具有由通过延迟模块的锁存输出的延迟时间确定的脉冲宽度 。 脉冲信号耦合到锁存模块，用于当脉冲信号未被确认时复位锁存模块。

公开(公告)号：US20060232904A1

公开(公告)日：2006-10-19

申请号：US11106303

申请日：2005-04-13

Applicant: Jui-Jen Wu ,  Yung-Lung Lin

Inventor： Jui-Jen Wu ,  Yung-Lung Lin

IPC: H02H5/04

CPC classification number: G11C17/18 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A sensing circuit is disclosed for sensing a programming state of an electrical fuse, comprising. An electrical fuse is coupled to a supply voltage. A first transistor is serially coupled between the electrical fuse and a complementary supply voltage. An inverter sense amplifier is coupled to a node between the electrical fuse and the first transistor for outputting a logic signal whose value is determined based on a comparison between a resistance of the electrical fuse and a predetermined reference resistance. A bias circuit applies a bias independent of variation of the first voltage to a gate of the first transistor, such that the predetermined reference resistance is substantially insensitive to the variation of the first voltage.

Abstract translation: 公开了用于感测电熔丝的编程状态的检测电路，包括： 电熔丝与电源电压耦合。 第一晶体管串联耦合在电熔丝和补充电源电压之间。 逆变器读出放大器耦合到电熔丝和第一晶体管之间的节点，用于输出基于电熔丝的电阻与预定参考电阻之间的比较来确定其值的逻辑信号。 偏置电路将独立于第一电压的变化的偏置施加到第一晶体管的栅极，使得预定参考电阻对第一电压的变化基本上不敏感。

公开(公告)号：US08619488B2

公开(公告)日：2013-12-31

申请号：US13492635

申请日：2012-06-08

Applicant: Yung-Lung Lin ,  Jui-Jen Wu ,  Shine Chung ,  Fu-Lung Hsueh

Inventor： Yung-Lung Lin ,  Jui-Jen Wu ,  Shine Chung ,  Fu-Lung Hsueh

IPC: G11C17/18 ,  G11C17/14 ,  G11C17/16 ,  G11C17/00

CPC classification number: G11C11/5692 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for programming a multi-level electrical fuse system comprises providing a fuse box with an electrical fuse and providing one of at least two fuse writing voltages to the electrical fuse to program the electrical fuse to one of at least two resistance states. The fuse box comprises at least one electrical fuse, a programming device serially coupled to the electrical fuse, and a variable power supply coupled to the fuse box and configured to generate two or more voltage levels.

Abstract translation: 一种用于编程多电平电熔丝系统的方法包括：提供具有电熔丝的保险丝盒，并向所述电熔丝提供至少两个熔丝写入电压中的一个，以将所述电熔丝编程为至少两个电阻状态之一。 保险丝盒包括至少一个电熔丝，串联耦合到电熔丝的编程装置，以及耦合到保险丝盒并配置成产生两个或多个电压电平的可变电源。