公开(公告)号：US20060224648A1

公开(公告)日：2006-10-05

申请号：US11094760

申请日：2005-03-30

申请人： J. Johnson

发明人： J. Johnson

IPC分类号： G06F1/02

CPC分类号： G06F7/556 ,  G06F1/0307

摘要： An apparatus for providing a base-2 logarithm approximation to a binary number is disclosed. A position k of the most significant bit within a binary number is located. Then, all bits that are less significant than position k within the binary number are assigned as a fractional portion of a base-2 logarithm approximation of the binary number. Next, a subset of the fractional portion is utilized to generate an adjustment value βm for the fractional portion. The numeric value k is then converted to a binary value representing an integer portion of the base-2 logarithm approximation of the binary number. Finally, the integer portion is added to the fractional portion along with the adjustment value βm for the fractional portion to form the base-2 logarithm approximation of the binary number.

摘要翻译： 公开了一种用于向二进制数提供基2对数近似的装置。 位于二进制数中最高有效位的位置k。 然后，将二进制数中的位置k以下的所有比特分配为二进制数的基数2对数近似的小数部分。 接下来，使用分数部分的子集来生成分数部分的调整值βm m。 然后将数值k转换为表示二进制数的基数2对数近似的整数部分的二进制值。 最后，将整数部分与分数部分的调整值βm相加到小数部分，以形成二进制数的基数2对数近似。

公开(公告)号：US20050273481A1

公开(公告)日：2005-12-08

申请号：US11142485

申请日：2005-06-01

申请人： Paul Dent

发明人： Paul Dent

IPC分类号： G06F1/02 ,  G06F7/48 ,  G06F7/483 ,  G06F7/556

CPC分类号： G06F7/556 ,  G06F7/4806

摘要： A method and ALU for implementing logarithmic arithmetic in a multi-stage pipeline is described herein. According to one embodiment, a master function is decomposed into two or more sub-functions. Memory associated with the pipeline stores a look-up table for each stage of the pipeline, where each table represents function values generated based on the corresponding sub-function, and where the look-up table associated with one stage differs from the look-up table(s) associated with at least one other stage. Each stage computes a stage output based on the stage input and the corresponding look-up table. By combining the stage outputs, the multi-stage pipeline outputs the logarithmic arithmetic output.

摘要翻译： 这里描述了用于在多级流水线中实现对数运算的方法和ALU。 根据一个实施例，主功能被分解成两个或更多个子功能。 与流水线相关联的存储器存储管道的每个级的查找表，其中每个表表示基于相应子功能生成的功能值，并且与一个级相关联的查找表与查找不同 与至少一个其他阶段相关联的表。 每个阶段基于舞台输入和相应的查找表来计算舞台输出。 通过组合级输出，多级流水线输出对数运算输出。

公开(公告)号：US20040184569A1

公开(公告)日：2004-09-23

申请号：US10769152

申请日：2004-01-30

发明人： Raghu Challa ,  Nitin Kasturi ,  Nikolai Schlegel

IPC分类号： H04L027/08

CPC分类号： G06F7/5235 ,  G06F1/0307 ,  G06F7/483 ,  G06F7/556

摘要： The invention is directed toward a digital VGA that is implemented in the logarithmic domain. The digital VGA exploits logarithmic properties to replace a complex multiplier of a conventional digital VGA with a simple and inexpensive adder. Moreover, additional techniques are described to significantly reduce the size of one or more lookup tables (LUTs) implemented within the digital VGA. In this manner, the invention can realize a simple, low cost digital VGA.

摘要翻译： 本发明涉及在对数域中实现的数字VGA。 数字VGA利用对数属性，用简单且便宜的加法器代替常规数字VGA的复数乘法器。 此外，描述了附加技术以显着减少在数字VGA内实现的一个或多个查找表（LUT）的大小。 以这种方式，本发明可以实现简单，低成本的数字VGA。

公开(公告)号：US20020124034A1

公开(公告)日：2002-09-05

申请号：US09754040

申请日：2000-12-27

发明人： Ronen Zohar

IPC分类号： G06F001/02 ,  G06F007/38

CPC分类号： G06F7/556 ,  G06F7/483

摘要： The present invention relates to a system and method to efficiently approximate the term 2X. The system includes an approximation apparatus to approximate 2X, wherein X is a real number. The system further includes a memory to store a computer program that utilizes the first approximation apparatus. The system also includes a central processing unit (CPU) that is cooperatively connected to the approximation apparatus and the memory, and that executes the computer program.

摘要翻译： 本发明涉及一种有效地近似术语2X的系统和方法。 该系统包括近似2X的近似装置，其中X是实数。 该系统还包括存储器，用于存储利用第一近似装置的计算机程序。 该系统还包括与近似装置和存储器协同连接并执行计算机程序的中央处理单元（CPU）。

公开(公告)号：US06317764B1

公开(公告)日：2001-11-13

申请号：US09267330

申请日：1999-03-12

申请人： Leonard D. Rarick

发明人： Leonard D. Rarick

IPC分类号： G06F738

CPC分类号： G06F7/556 ,  G06F7/548

摘要： The invention provides a method and system for computing transcendental functions quickly: (1) the multiply ALU is enhanced to add a term to the product, (2) rounding operations for intermediate multiplies are skipped, and (3) the Taylor series is separated into two partial series which are performed in parallel. Transcendental functions with ten terms (e.g., SIN or COS), are thus performed in about ten clock times.

摘要翻译： 本发明提供了一种快速计算超越函数的方法和系统：（1）增加乘法ALU以向产品添加项，（2）跳过中间乘数的舍入运算，（3）泰勒级数分为 并行执行两个部分系列。 因此，在十个时钟内执行具有十个术语（例如，SIN或COS）的超验功能。

公开(公告)号：US06295014B1

公开(公告)日：2001-09-25

申请号：US09177945

申请日：1998-10-23

申请人： Peter Charles Eastty ,  Peter Damien Thorpe ,  Christopher Sleight

发明人： Peter Charles Eastty ,  Peter Damien Thorpe ,  Christopher Sleight

IPC分类号： H03M300

CPC分类号： H03M7/3013 ,  G06F7/556

摘要： An audio signal processor for processing 1-bit signals, comprises an input 40 for receiving a 1-bit signal, means 41, 42 for applying a predetermined filter characteristic to the 1-bit signal whereby the signal is also converted to an n-bit signal where n is greater than one, means 43 for determining the absolute value of the n-bit signal, means 46, 51 for producing a dynamics control signal dependent on the said absolute value, means 48 for applying the dynamics control signal to the 1-bit input signal, and means 49 for requantizing the dynamics controlled signal as a 1-bit signal and shaping the noise in the requantised 1-bit signal. Circuits for producing LOG base 2 and the corresponding anti-log are also disclosed.

摘要翻译： 用于处理1位信号的音频信号处理器包括用于接收1位信号的输入端40，用于对1位信号施加预定的滤波特性的装置41,42，由此信号也被转换成n位 信号，其中n大于1，用于确定n位信号的绝对值的装置43，用于产生取决于所述绝对值的动力学控制信号的装置46,51，用于将动态控制信号施加到1 以及用于将动态控制信号重新量化为1位信号的装置49，并对重新量化的1位信号中的噪声进行整形。 还公开了用于生成LOG基础2的电路和相应的反对数。

公开(公告)号：US06182100B2

公开(公告)日：2001-01-30

申请号：US09106942

申请日：1998-06-30

申请人： Martin Stanley Schmookler

发明人： Martin Stanley Schmookler

IPC分类号： G06F738

CPC分类号： G06F7/483 ,  G06F7/556

摘要： A method for performing a logarithmic estimation on a positive floating-point number within a data processing system is disclosed. A floating-point number includes a sign bit, multiple exponent bits, and a mantissa having an implied one and multiple fraction bits. A fraction part of an estimate is obtained via a table lookup utilizing the fraction bits of the floating-point number as input. An integer part of the estimate is obtained by converting the exponent bits to an unbiased representation. The integer part is then concatenated with the fraction part to form an intermediate result. Subsequently, the intermediate result is normalized to yield a mantissa, and an exponent part is produced based on the normalization. Finally, the exponent part is combined with the mantissa to form a floating-point result.

摘要翻译： 公开了一种对数据处理系统内的正浮点数执行对数估计的方法。 浮点数包括符号位，多个指数位和具有隐含的一个和多个分数位的尾数。 通过使用浮点数的分数比特作为输入的表查找获得估计的分数部分。 通过将指数位转换为无偏表示来获得估计的整数部分。 然后将整数部分与分数部分连接以形成中间结果。 随后，中间结果被归一化以产生尾数，并且基于归一化产生指数部分。 最后，指数部分与尾数组合形成浮点运算结果。

公开(公告)号：US5963460A

公开(公告)日：1999-10-05

申请号：US768781

申请日：1996-12-17

申请人： Leonard D. Rarick

发明人： Leonard D. Rarick

IPC分类号： G06F7/544 ,  G06F7/548 ,  G06F7/556 ,  G06F7/38 ,  G06F7/50 ,  G06F7/52

CPC分类号： G06F7/556 ,  G06F7/548

摘要： The invention provides a method and system for computing transcendental functions quickly: (1) the multiply ALU is enhanced to add a term to the product, (2) rounding operations for intermediate multiplies are skipped, and (3) the Taylor series is separated into two partial series which are performed in parallel. Transcendental functions with ten terms (e.g., SIN or COS), are thus performed in about ten clock times.

公开(公告)号：US5726924A

公开(公告)日：1998-03-10

申请号：US680282

申请日：1996-07-11

申请人： John Michael Buss ,  James Douglas Dworkin ,  Scott Edward Lloyd ,  ShaoWei Pan ,  Stephen L. Smith ,  Shay-Ping Thomas Wang

发明人： John Michael Buss ,  James Douglas Dworkin ,  Scott Edward Lloyd ,  ShaoWei Pan ,  Stephen L. Smith ,  Shay-Ping Thomas Wang

IPC分类号： G06F7/552 ,  G06F7/556 ,  G06F1/02 ,  G06F7/00 ,  G06F7/50 ,  G06F15/00

CPC分类号： G06F7/556

摘要： A circuit and method for computing an exponential signal x.sup.g is provided. The circuit includes a logarithm converter which converts an input signal to binary word that represents the logarithm of an input signal x. A first shift register shifts the binary word in a bit-wise fashion to produce a first intermediate value; while a second shift register shifts the binary word in a bit-wise fashion to produce a second intermediate value. The shift registers may be implemented using multiplexers. The shifting operations are equivalent to multiplying the intermediate values by a factor which is a power of two. The first intermediate value is either added to or subtracted from the second intermediate value to produce a combined value. An inverse-logarithm converter converts the combined value to the exponential signal.

公开(公告)号：US5463574A

公开(公告)日：1995-10-31

申请号：US99119

申请日：1993-07-29

申请人： Bernard Desrosiers ,  Didier Louis ,  Didier Pinchon ,  Andre Steimle

发明人： Bernard Desrosiers ,  Didier Louis ,  Didier Pinchon ,  Andre Steimle

IPC分类号： G06F7/556 ,  G06F7/38

CPC分类号： G06F7/556 ,  G06F7/49947

摘要： An apparatus for executing argument reduction in the computation of F(x)=2**x-1 (with .vertline.x.vertline.

摘要翻译： 一种用于在F（x）= 2 ** x-1（具有| x | <1）的计算中执行参数减少的装置，根据IEEE 754标准浮点型确定xi的值和计算（x-xi） 点格式具有第一电路装置，其可操作以对N位尾数执行流水线操作; 第一电路装置的输出连接到N + 4位的归一化电路，其三个最左边的输入被连接到“零”，并且其三个最左边的位J（0：2） 位总线（J-BUS）。 还包括一个领先的零检测器/编码器电路和第二电路装置，其可操作用于对输出控制对准器电路的编码器电路的指数执行流水线操作，以及由检测器/编码器电路和编码器电路的输出驱动的选择器电路 其输出控制归一化电路; xi确定电路，其在连接到第一电路装置的xi-BUS上产生xi尾数，使得：尾数xi = 0 = K（1）K（2）1 0。 。 。 ，以及用于存储F（xi）值的只读存储器，其输出连接到用于F（xi）的相应尾数和指数部分的第一和第二电路的输入。