公开(公告)号：US4497976A

公开(公告)日：1985-02-05

申请号：US466628

申请日：1983-02-15

申请人： Norbert Torggler ,  Dietmar Franz

发明人： Norbert Torggler ,  Dietmar Franz

IPC分类号： H04L12/52 ,  H04L13/08

CPC分类号： H04L12/52

摘要： Additional information is transmitted, in conjunction with message signals which are transmitted over a data switching center belonging to a public switched network. The data switching center is connected to teleprinter subscriber stations and teletex subscriber stations which are capable of transmitting and receiving message signals in accordance with different transmission procedures. The transmission of message signals between the subscriber stations occurs over at least one signal converter connected to the data switching center. After an occupation of the signal converter proceeding from a teleprinter subscriber station, the corresponding digital information are deposited in a memory of the signal converter by the data switching center upon each attempt to establish a connection from the signal converter to a teletex subscriber station. Under certain conditions, together with the message signal transmitted by the teleprinter subscriber station and contained in the signal converter, the additional information are emitted from the memory to the teletex subscriber station after a successful completion of a connection between the signal converter and the teletex subscriber station.

摘要翻译： 结合通过属于公共交换网络的数据交换中心发送的消息信号来传送附加信息。 数据交换中心连接到能够根据不同传输过程发送和接收消息信号的电传打印机用户台和电信用户台。 消息信号在用户站之间的传输发生在连接到数据交换中心的至少一个信号转换器上。 在从电传打印机用户站进行的信号转换器的占用之后，当每次尝试建立从信号转换器到teletex用户站的连接时，相应的数字信息由数据交换中心存储在信号转换器的存储器中。 在特定条件下，连同电传打印机用户台发送并包含在信号转换器中的消息信号，在信号转换器和teletex用户之间的连接成功完成之后，附加信息从存储器发送到teletex用户站 站。

公开(公告)号：US4485470A

公开(公告)日：1984-11-27

申请号：US388746

申请日：1982-06-16

申请人： Peter A. Reali

发明人： Peter A. Reali

IPC分类号： H04L12/52 ,  H04J3/06

CPC分类号： H04L12/525

摘要： This invention is a data line interface providing a parallel to serial conversion technique for selectively increasing serial data transmission rates. The data line interface receives a 16-bit data word or signal from a TDM bus and transmits it serially to one of a plurality of data terminal interfaces depending on which one is selected. The invention utilizes a double buffer receiver circuit to determine when to speed up the destination transmission clock.The asynchronous data line interface looks at the value of each of the bits in the data word by sampling the center of each bit. However, during the stop bit, it will not look at the value after sampling the center. Thus, during the time that would have been devoted to the last half of the stop bit, a new start bit may be accepted, allowing the speed up of data to occur.

摘要翻译： 本发明是提供并行到串行转换技术的数据线接口，用于选择性地提高串行数据传输速率。 数据线接口从TDM总线接收16位数据字或信号，并根据选择哪一个将其串行发送到多个数据终端接口之一。 本发明利用双缓冲接收机电路来确定何时加速目的地传输时钟。 异步数据线接口通过对每个位的中心进行采样来查看数据字中每个位的值。 但是，在停止位期间，它不会在取样中心后看到值。 因此，在停止位的最后一半的时间内，可以接受新的起始位，从而允许数据的加速发生。

公开(公告)号：US4428042A

公开(公告)日：1984-01-24

申请号：US231455

申请日：1981-02-04

申请人： Dieter Niethhammer ,  Robert Eggertsberger ,  Gerhard Wilmers

发明人： Dieter Niethhammer ,  Robert Eggertsberger ,  Gerhard Wilmers

IPC分类号： H03M5/08 ,  G06F13/38 ,  H04J3/06 ,  H04J3/16 ,  H04L12/52 ,  H04Q11/04 ,  G06F3/00 ,  G06F15/16

CPC分类号： H04Q11/04 ,  H04J3/062 ,  H04J3/1682 ,  H04L12/525

摘要： A coupling device provides for an inexpensive coupling between two data processing systems at a relatively low expense, even when a large number of channels is involved. The coupling device provides, for each data processing system, a clock pulse line, a transmitting bus, a receiving bus and an address bus. For each address, two memory cells are provided and have associated address decoders. The address decoders receive the addresses by way of the address buses and with identification of an associated address, transmit decoding signals to the memory cells. A pair of clock pulse controls provide sequences of write commands and read commands for controlling the writing of individual bits of the two transmitting buses into the addressed memory cells and cause transfer of these bits to the receiving buses.

摘要翻译： 耦合装置即使在涉及大量信道时，以相对低的成本提供两个数据处理系统之间的廉价耦合。 耦合装置为每个数据处理系统提供时钟脉冲线，发送总线，接收总线和地址总线。 对于每个地址，提供两个存储单元并具有相关联的地址解码器。 地址解码器通过地址总线和相关地址的识别来接收地址，将解码信号发送到存储器单元。 一对时钟脉冲控制提供写入命令和读取命令的顺序，用于控制两个发送总线的各个位的写入到寻址的存储器单元中并且使这些位传送到接收总线。

公开(公告)号：US4413338A

公开(公告)日：1983-11-01

申请号：US244170

申请日：1981-03-16

申请人： Roger Renoulin ,  Jean-Yves Le Brun

发明人： Roger Renoulin ,  Jean-Yves Le Brun

IPC分类号： H04Q3/545 ,  H04L12/52 ,  H04L12/56 ,  H04Q3/60 ,  H04Q11/04 ,  H04J3/16 ,  H04J6/00

CPC分类号： H04L12/56 ,  H04L12/525

摘要： A communications system interconnects a number of asynchronous data processing terminals, operating at different speeds among themselves, with a high speed switching or communication network. The system uses as a time multiplexed loop linking terminals which are later duplicated for security reasons. The number of terminals that may be hooked up may exceed that which would be provided if all terminals were to be active simultaneously. For this purpose, a signalling or watch function is used in the system to monitor the state of each terminal. This function, which assumes the active (busy) or rest (idle) state of the terminals, is based on a low speed search for terminals at rest, on detecting the change in their states and on the time sharing allocation, of the time multiplexed transmission resource among the active terminals according to their needs. The time sharing of the transmission resource is adaptive.

摘要翻译： 通信系统将多个以不同速度工作的异步数据处理终端与高速交换或通信网络相互连接。 该系统用作连接终端的时间复用环路，由于安全原因，终端被复制。 如果所有终端同时处于活动状态，则可能连接的终端数量可能会超过提供的终端数量。 为此，在系统中使用信令或监视功能来监视每个终端的状态。 假设终端的活动（忙）或休眠（空闲）状态的该功能基于对休眠终端的低速搜索，在检测到其状态的变化和时间分配的时间复用 活动终端之间的传输资源根据需要。 传输资源的时间共享是自适应的。

公开(公告)号：US4160128A

公开(公告)日：1979-07-03

申请号：US918429

申请日：1978-06-23

申请人： Alain G. Texier

发明人： Alain G. Texier

IPC分类号： H04J3/00 ,  H04J3/06 ,  H04J3/24 ,  H04L12/52 ,  H04J3/02

CPC分类号： H04J3/0629 ,  H04J3/24 ,  H04L12/52

摘要： Digital transmission system providing multipoint connections in which a main data transceiver can communicate with a plurality of secondary data transceivers and the secondary data transceivers can each, in turn, communicate with the main data transceiver, transmission occurring via component digital words at certain low rates multiplexed into intermediate rate incoming digital channels which are themselves multiplexed into a high rate incoming highway. The words are given a first partial address in the low to intermediate rate multiplexing step and a second partial address in the intermediate to high rate multiplexing step. A digital switching network is provided for selectively switching the component words from the high rate incoming highway to word positions in a high rate outgoing highway according to their first and second partial addresses. A multipoint unit is connected to the switching network by intermediate rate incoming and outgoing digital channels and the high rate highway. The multipoint unit comprises means for simultaneously transferring the input words assigned to the main transceiver on the intermediate rate incoming digital channel to output word positions assigned to the secondary transceivers on the intermediate rate outgoing digital channel and means for sequentially transferring the input words assigned to the secondary transceivers on the intermediate rate incoming digital channel to output word positions assigned to the main transceiver on the intermediate rate outgoing digital channel.

摘要翻译： 该装置在数字分配器（7）之间建立多点链路，以便连接主数据收发器（1）与多个辅助数据收发器（2-5）。 次级收发器可以与主收发器进行通信。 数据传输在数字线路（10-50）上以低速率传输的数字信封中进行，这些数字信封不同于彼此的倍数，它们根据中间速率双向数字 线（110-130）。 信封的第一位是形成伪随机序列的地址位。 链接到分配器（7）的多点单元（8）使得可以形成与从主收发器接收的包络相同的次级复制信封，因为存在次级收发器，并且将地址位重新分配给次级复制信封作为 目的地二次收发器的功能。

公开(公告)号：US4068098A

公开(公告)日：1978-01-10

申请号：US654021

申请日：1976-01-30

申请人： Per-Olof Thyselius

发明人： Per-Olof Thyselius

IPC分类号： H04L5/22 ,  H04L12/52 ,  H04Q11/04 ,  H04J3/16

CPC分类号： H04L12/52 ,  H04L5/22 ,  H04Q11/04

摘要： A method of and an apparatus is disclosed for economically addressing memory positions in a switch memory of a transit exchange for the transfer of synchronous data signals between incoming and outgoing TDM links comprising data channels of several data rates, each constituting a multiple of a basic rate derived from the number of time slots in a TDM frame. The data signals are stored in a switch memory having a memory position for each of the data channels in the incoming links and are then transferred to a buffer memory having a memory position for each time slot of the data channels in the outgoing links before they are sent out on these links. The memory writing as well as the reading occurring at a repetition rate determined by the data rate of the respective data channel. The data signals are written into the switch memory by the aid of an address calculator including a structure memory for the storage of information indicating the allocation of time slots to the various data channels of each link, which information is common to all links of the same type, and a type memory for the storage of type designations where the relevant type designation is addressed by means of the identity number of the link.

摘要翻译： 公开了一种用于经济地寻址中转交换机的交换存储器中的存储器位置的方法和装置，用于在包括几个数据速率的数据信道的多个数据速率的输入和输出TDM链路之间传送同步数据信号，每个数据信道构成基本速率的倍数 从TDM帧中的时隙数导出。 数据信号被存储在具有用于输入链路中的每个数据信道的存储器位置的开关存储器中，然后被传送到具有在输出链路中的数据信道的每个时隙的存储位置的缓冲存储器 发送到这些链接。 存储器写入以及以由相应数据信道的数据速率确定的重复率发生的读取。 数据信号借助于地址计算器被写入开关存储器，该地址计算器包括用于存储指示每个链路的各种数据信道的时隙分配的信息的结构存储器，该信息对于相同的所有链路是共同的 类型和用于存储类型名称的类型存储器，其中通过链接的身份号来寻址相关类型标识。

公开(公告)号：US3984641A

公开(公告)日：1976-10-05

申请号：US493024

申请日：1974-07-30

申请人： Hinrich Ruyter

发明人： Hinrich Ruyter

IPC分类号： H04J3/06 ,  H04L12/52 ,  H04L25/05 ,  H04Q11/04

CPC分类号： H04J3/0626 ,  H04L12/525 ,  H04L25/05 ,  H04Q11/04

摘要： A system is disclosed for safeguarding data against slip in signals occurring in interfaces between exchanges employing different exchange clock rates. Suitably connected storage arrangements cause the instants of slip compensation in both directions of transmission to coincide. In this way, omission of a signal in one direction of transmission results in a signal being inserted in the other direction and prevents the loss of data.

摘要翻译： 公开了一种用于保护数据以防止在采用不同交换时钟速率的交换机之间的接口中发生的信号中的滑移的系统。 适当连接的储存装置会使传动两个方向的滑差补偿时刻一致。 以这种方式，在一个传输方向上省略信号导致信号沿另一个方向插入并防止数据丢失。

公开(公告)号：US3952162A

公开(公告)日：1976-04-20

申请号：US581081

申请日：1975-05-27

申请人： Alain G. Texier ,  Michel R. Davancens

发明人： Alain G. Texier ,  Michel R. Davancens

IPC分类号： H04J3/00 ,  H04L12/52 ,  H04Q11/04

CPC分类号： H04J3/0611 ,  H04L12/52

摘要： A time division digital switching network comprises first multiplexing means in which first-order digital data channels transmitting words consisting of a given number of bits and having first rates which are different from but multiples of one another undergo a first multiplexing converting them into a second-order digital data channels having a second predetermined rate. Thereafter there are provided second multiplexing means in which the second-order digital channels undergo a second multiplexing converting them into third-order digital data channels having a third predetermined rate. In a digital switching unit having at least one buffer store, the first-order-channel words multiplexed into the third-order channels are grouped at an address whose first part depends upon the second-order channel they occupy in the third-order channel and whose second part depends upon the first-order channel they occupy in the second-order channel. The bits of a given rank of the words of a second-order channel form a pseudorandom sequence having a known period and, therefore, the bits of a given rank of the words of a third-order channel form a number of interleaved pseudorandom sequences. The digital switching unit includes means for separating the interleaved pseudorandom sequences and for deducing from the bits composing them the second part of the address of the words.

摘要翻译： 时分数字交换网络包括第一多路复用装置，其中传送由给定数量的比特组成的具有第一速率的一阶数字数据信道，其中第一速率彼此不同但是彼此的倍数经过第一复用，将它们转换为第二复用装置， 具有第二预定速率的数字数据通道。 此后，提供第二多路复用装置，其中二阶数字信道进行第二复用，将它们转换成具有第三预定速率的三阶数字数据信道。 在具有至少一个缓冲存储器的数字切换单元中，多路复用到三阶信道中的一阶通道字被分组在其第一部分取决于它们在三阶信道中占据的二阶信道的地址， 其第二部分取决于他们在二级渠道中占据的一级渠道。 二阶通道的字的给定秩的位形成具有已知周期的伪随机序列，因此，三阶通道的字的给定秩的位形成交错的伪随机序列的数目。 数字切换单元包括用于分离交织的伪随机序列和从构成它们的比特中排除词的地址的第二部分的装置。

公开(公告)号：US3920916A

公开(公告)日：1975-11-18

申请号：US40153473

申请日：1973-09-27

申请人： STROMBERG CARLSON CORP

发明人： BRIGHTMAN BARRIE ,  DATSKO GEORGE ,  MOLL EDWARD W ,  STEWART WILLIAM H

IPC分类号： H04L12/52 ,  H04Q11/04

CPC分类号： H04Q11/0407 ,  H04L12/525

摘要： A digital switching network including send memory circuits and receive memory circuits interconnected by highways. The send memory circuit receives and stores said time divided multiplex signals and transmits the same on a time divided multiplex basis to the interconnect highways at any of a plurality of recurring time slots including those assigned to the send time divided multiplex signals. The receive memory receives and stores the time divided multiplex signals from the interconnect highways and transmits the same to the receive circuits at appropriate receive time slots. Control circuits provide for the interconnection of any send and receive lines. Data for establishing interconnection is received by register circuits in binary form. A free time slot is selected by the control circuits for the transmission of the send time divided multiplex signals over any of the interconnecting highway. The send and receive memory circuits are controlled by recirculating memories supplied by data from the register means. Single or duplex connections can be established. A trace circuit is provided for identifying a selected connection or identifying a series of busy connections.

公开(公告)号：US3909511A

公开(公告)日：1975-09-30

申请号：US50862074

申请日：1974-09-23

申请人： SIEMENS AG

发明人： KAMMERL ANTON ,  SCHAFFER BERNHARD

IPC分类号： H04L12/52 ,  H04Q3/545 ,  H04L11/00 ,  H04Q3/64

CPC分类号： H04Q3/545 ,  H04L12/52

摘要： A program controlled data switching system wherein the connection circuits include storage devices and gate switching elements; the transfer of items of information occurring on the lines into the storage devices is controlled in groups by means of a central interrogation pulse train. Initially gate switching elements emit a request criterion; to identify the connection circuits transmitting a request criterion, for each position or digit of the code used to characterize the connection circuits there is provided a series of decentralized identification devices which are arranged in stages in accordance with the known coordinate principle, and are connected to one another via request and resetting lines; means are provided to code and store the identification result.

摘要翻译： 一种程序控制数据交换系统，其中所述连接电路包括存储设备和门开关元件; 通过中央询问脉冲串将组中发生的信息项转移到存储装置中。 最初门开关元件发出请求标准; 为了识别发送请求标准的连接电路，对于用于表征连接电路的代码的每个位置或数字，提供了一系列分散式识别装置，它们根据已知的坐标原理分阶段布置，并且连接到 通过请求和重新设置线路; 提供了编码和存储识别结果的手段。