公开(公告)号：US10368115B2

公开(公告)日：2019-07-30

申请号：US15007042

申请日：2016-01-26

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Tadamasa Toma ,  Noritaka Iguchi ,  Hisaya Katou

IPC: H04N7/173 ,  H04N21/262 ,  H04N21/234 ,  H04N21/242 ,  H04N21/8547 ,  H04N21/858 ,  H04N21/236 ,  H04N21/2365 ,  H04N21/235 ,  H04N21/84 ,  H04N21/43

Abstract: A transmitting method according to one aspect of the present disclosure includes transmitting a first stream, the first stream including: timing update identification information id1 indicating whether or not a correspondence relationship between a first reference clock and a second reference clock has been updated, the first reference clock being used to transmit and receive the first stream, and the second reference clock being used to transmit and receive a second stream related to another content to be reproduced in synchronization with the content related to the first stream; a first time according to the first reference clock; and a second time according to the second reference clock, the second time being associated with the first time based on the updated correspondence relationship.

公开(公告)号：US10321200B2

公开(公告)日：2019-06-11

申请号：US15956301

申请日：2018-04-18

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Noritaka Iguchi ,  Tadamasa Toma ,  Hisaya Katou

IPC: H04N7/20 ,  H04N21/643 ,  H04L29/12 ,  H04L29/06 ,  H04N21/242 ,  H04N21/43 ,  H04N21/61 ,  H04N21/845 ,  H04L29/10 ,  H04N21/8547 ,  H04J3/06

Abstract: A transmission method includes: generating one or more transfer frames that each store one or more streams used for content transfer; and transmitting the one or more generated frames through broadcast, each of the one or more streams storing one or more second transfer units, each of the one or more second transfer units storing one or more first transfer units, and each of the one or more first transfer units storing one or more Internet Protocol (IP) packets. In at least one stream among the one or more streams, each of the first transfer units positioned at a head contains reference clock information indicating time used for reproduction of the content.

公开(公告)号：US10264232B2

公开(公告)日：2019-04-16

申请号：US15690362

申请日：2017-08-30

Applicant: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA

Inventor： Hiroshi Yahata ,  Tadamasa Toma

IPC: H04N9/87 ,  H04N9/82 ,  H04N21/44 ,  H04N21/432 ,  H04N21/426 ,  H04N21/488 ,  G11B27/32 ,  G11B27/30 ,  G11B27/34 ,  H04N9/804 ,  G11B20/12 ,  H04N5/85 ,  G11B20/10 ,  G11B27/28

Abstract: A recording medium according an aspect of the present disclosure has recorded therein a main video stream where a main video has been encoded, and a sub-video stream where a sub-video, that is to be superimposed on the main video and displayed, has been encoded. The sub-video stream includes bitmap data indicating a design of the sub-video and palette data specifying the display color of the design. The palette data includes first palette data for a first luminance dynamic range (SDR), and second palette data for a second luminance dynamic range (HDR) that is broader than the first dynamic range.

公开(公告)号：US09984726B2

公开(公告)日：2018-05-29

申请号：US14951759

申请日：2015-11-25

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Tadamasa Toma ,  Noritaka Iguchi ,  Takahiro Nishi ,  Hisaya Katou

IPC: G11B27/10 ,  H04N19/44 ,  H04N19/70 ,  H04N21/43 ,  H04N21/242 ,  H04N21/643 ,  H04N21/845 ,  H04N21/8547

CPC classification number: G11B27/10 ,  H04N21/242 ,  H04N21/43 ,  H04N21/4302 ,  H04N21/643 ,  H04N21/8456 ,  H04N21/8547

Abstract: A data transmission method according to one aspect of the present disclosure includes: generating a plurality of MPUs, reference clock time information, and leading clock time information indicating a leading PTS that is a clock time at which a leading access unit in the MPU is presented, transmitting the generated plurality of MPUs, reference clock time information, and leading clock time information, wherein the leading clock time information indicates the leading PTS of the plurality of MPUs of which presentation is started after the leading clock time information is transmitted in the generated plurality of MPUs, and each of the generated plurality of MPUs indicates a time point at which each access unit that does not exist in a head of the MPU is presented as a relative value to a time point of another access unit in the MPU.

公开(公告)号：US12284376B2

公开(公告)日：2025-04-22

申请号：US17673039

申请日：2022-02-16

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Virginie Drugeon ,  Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/46 ,  H04N19/105 ,  H04N19/169 ,  H04N19/172 ,  H04N19/423 ,  H04N19/44

Abstract: An encoder includes circuitry and memory coupled to the circuitry. In operation, the circuitry encodes, per temporal sub-layer, one or more hypothetical reference decoder (HRD) parameters into an HRD-related supplemental enhancement information (SEI) message, the one or more HRD parameters being one or more parameters for an HRD, the one or more parameters being related to a decoding unit, the HRD-related SEI message being an SEI message related to the HRD.

公开(公告)号：US12267521B2

公开(公告)日：2025-04-01

申请号：US18383205

申请日：2023-10-24

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Ryuichi Kanoh ,  Tadamasa Toma ,  Kiyofumi Abe ,  Takahiro Nishi

IPC: H04N19/52 ,  H04N19/122 ,  H04N19/124 ,  H04N19/176 ,  H04N19/44

Abstract: An encoder includes circuitry and memory. Using the memory, the circuitry performs a primary transform on a derived prediction error, performs a secondary transform on a result of the primary transform, quantizes a result of the secondary transform, and encodes a result of the quantization as data of an image. When a current block to be processed has a predetermined shape, the encoder performs the secondary transform using, among secondary transform basis candidates that are secondary bases usable in the secondary transform, only a secondary transform basis candidate having a size that is not largest size containable in the current block.

公开(公告)号：US12262058B2

公开(公告)日：2025-03-25

申请号：US18231933

申请日：2023-08-09

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Masato Ohkawa ,  Hideo Saitou ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Yusuke Kato

IPC: H04N19/112 ,  H04N19/119 ,  H04N19/12 ,  H04N19/16 ,  H04N19/17 ,  H04N19/184 ,  H04N19/186 ,  H04N19/30 ,  H04N19/60

Abstract: Provided is an encoder including: circuitry; and memory coupled to the circuitry. In operation, the circuitry: performs a mapping process of Luma Mapping with Chroma Scaling (LMCS) for transforming a first pixel value space applied to a luma display image signal into a second pixel value space applied to a luma encoding process signal, using line segments forming a transform curve, each of which corresponds to a different one of sections obtained by partitioning the first pixel value space; and encodes an image, and in the performing of the LMCS, the circuitry determines the transform curve so that among boundary values in the second pixel value space, a first value obtained by dividing a boundary value by a base width defined according to a bit depth of the image is not equal to a second value obtained by dividing another boundary value by the base width.

公开(公告)号：US20250097438A1

公开(公告)日：2025-03-20

申请号：US18968220

申请日：2024-12-04

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Takahiro Nishi ,  Tadamasa Toma ,  Kiyofumi Abe ,  Ryuichi Kanoh

IPC: H04N19/31 ,  H04N19/117 ,  H04N19/172

Abstract: An encoder which encodes a video including a plurality of pictures includes circuitry and memory. Using the memory, the circuitry performs: encoding a first picture among the plurality of pictures; and performing (i) a first operation for encoding a parameter set for a second picture which follows the first picture in coding order among the plurality of pictures after encoding the first picture, and encoding the second picture after encoding the parameter set, or (ii) a second operation for encoding the second picture without encoding the parameter set after encoding the first picture. The circuitry performs the first operation when the second picture is a determined picture, in the performing of the first operation or the second operation.

公开(公告)号：US12244809B2

公开(公告)日：2025-03-04

申请号：US17527546

申请日：2021-11-16

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Yusuke Kato ,  Takahiro Nishi ,  Tadamasa Toma ,  Kiyofumi Abe

IPC: H04N19/13 ,  H04N19/176 ,  H04N19/18 ,  H04N19/46 ,  H04N19/60

Abstract: An encoder including circuitry and memory coupled to the circuitry. In both of a first case where an orthogonal transform is performed and a second case where the orthogonal transform is skipped, when a number of CABAC processes is within an allowable range, the circuitry: encodes a plurality of coefficient information flags by CABAC; and encodes a remainder value of the coefficient; and when the number of CABAC processes is not within the allowable range, the circuitry: skips the encoding of the plurality of coefficient information flags, wherein in the first case, the circuitry: converts the coefficient to a second coefficient by using a poszero value that is determined using a plurality of surrounding coefficients; and encodes a value of the second coefficient, and wherein in the second case, the circuitry: encodes the value of the coefficient.

公开(公告)号：US20250071316A1

公开(公告)日：2025-02-27

申请号：US18949089

申请日：2024-11-15

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Virginie DRUGEON ,  Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Ryuichi Kanoh

IPC: H04N19/513 ,  H04N19/176 ,  H04N19/182 ,  H04N19/196

Abstract: An encoder is an encoder that encodes a block in a picture using a prediction image of the block, and includes circuitry and memory. Using the memory, the circuitry: calculates a first average pixel value which is an average pixel value of first reference samples out of the first reference samples and second reference samples, The first reference samples are referable and located outside the block and adjacent to a first side of the block. The second reference samples are referable and located outside the block and adjacent to a second side of the block. When generating the prediction image, the circuitry applies the same prediction pixel value to inner samples among current samples to be processed that are included in the block. The inner samples constitute a quadrilateral region including at least two current samples in each of a horizontal direction and a vertical direction.