Abstract:
Methods and systems are described for enabling display system data transmission during use. An integrated circuit package includes input interface circuitry configured to receive an audio-video data stream having a video signal and timing information and timing extraction circuitry that can identify blanking patterns for the video signal. The package includes input processing circuitry for receiving audio-video signal and converting the audio-video data stream input into a low voltage differential signal (LVDS). The package includes a timing controller having timing extraction circuitry, a set of symbol buffers, a scheduler, and timing control circuitry. All configured to implement LVDS data transfer and in some implementation enable point to point data transfer from data buffers to associated column drivers.
Abstract:
In accordance with an embodiment, a network device includes a network controller and at least one network interface coupled to the network controller that includes at least one media access control (MAC) device configured to be coupled to at least one physical layer interface (PHY). The network controller may be configured to determine a network path comprising the at least one network interface that has a lowest power consumption of available media types coupled to the at least one PHY.
Abstract:
A method and circuit are disclosed for enabling an oscillator circuit to oscillate a predetermined period of time following completion of a power-up operation. The circuit may include a counter having a control for receiving a control signal from a system power-on-reset circuit, and a clock input. A ring oscillator has an output coupled to the clock input of the counter.
Abstract:
An integrated circuit for a smart card may include a transceiver and a controller for cooperating with the transceiver to receive operating requests from a host device. The controller may perform smart card operations based upon respective operating requests. Moreover, the controller also may cooperate with the transceiver to receive at least one advance request from the host device to indicate that at least one operating request will follow. By way of example, the standby operation may include loading data in at least one buffer, which may be sent to the host device based upon receiving the at least one operating request. Other standby operations may include disabling data transmission to the host device, such as when the communications bus of the host device is preoccupied, and ceasing performing a current smart card operation to allow a higher priority smart card operation to be performed, for example.
Abstract:
A compound camera system comprising component cameras that generate image data of an object and a processor that receives first image data from a first component camera and second image data from a second component camera and generates a virtual image. The processor projects virtual pixel data (u,v) to generate point data (x,y,z) located at depth, znullZ1, of a object plane of the object and projects the said point data (x,y,z) to generate first pixel data (u1,v1) located at a image plane of the first image. The processor also projects said point data (x,y,z) located at the depth, znullZ1, of the said object plane to generate second pixel data (u2,v2) located at the second image. The processor generates the virtual image by combining the color of first pixel data (u1,v1) and the color of second pixel data (u2,v2)
Abstract:
A testable, pulse-triggered static flip-flop. A pulse generator produces a data enable trigger pulse only when a test enable input is low, and a scan test enable trigger pulse only when a test enable input is high. The data enable trigger pulse controls the data input to the flip-flop, while the scan test enable trigger pulse controls the scan test input to the flip-flop. The flip-flop consists of a selection circuit comprised of two latches, each including an inverter and a transmission gate. One latch receives the data input and the other latch receives the scan test input. The data enable trigger pulse controls the transmission gate receiving the data input, and the scan test trigger pulse controls the transmission gate receiving the scan test input. The flip-flop also includes a keeper circuit consisting of a feedback inverter and a static latch.
Abstract:
A method for synthesizing a domino logic circuit design (18) from a source circuit definition (14) using a static logic circuit synthesis tool (12) includes generating a preliminary domino logic circuit (26) design using the circuit synthesis tool (12) and optimizing an attribute of the preliminary domino logic circuit design by substituting a static cell design for a domino cell design having a same function in the preliminary domino logic circuit design (30).
Abstract:
There is disclosed a voltage controlled oscillator (VCO) that receives nullV(IN) and nullV(IN) control voltages and outputs a VCO output signal having an oscillation frequency determined by the nullV(IN) and nullV(IN) control voltages. The VCO comprises: 1) a storage capacitor charged linearly by a constant charge current and discharged linearly by a constant discharge current; 2) a comparator for comparing the storage capacitor voltage to an upper threshold voltage and a lower threshold voltage. The comparator output drops to a negative saturation voltage (nullV(SAT)) when the storage capacitor voltage rises above the upper threshold voltage and rises to a positive saturation voltage (nullV(SAT)) when the storage capacitor voltage drops below the lower threshold voltage. The VCO also comprises: 3) a constant charge current source for injecting the constant charge current into the storage capacitor when the comparator output rises to the positive saturation voltage; and 4) a constant discharge current source for draining the constant discharge current from the storage capacitor when the comparator output drops to the negative saturation voltage.
Abstract:
Clustered VLIW processing elements, each preferably simple and identical, are coupled by a runtime reconfigurable inter-cluster interconnect to form a coprocessor executing only those portions of a program having high instruction level parallelism. The initial portion of each program segment executed by the coprocessor reconfigures the interconnect, if necessary, or is skipped. Clusters may be directly connected to a subset of neighboring clusters, or indirectly connected to any other cluster, a hierarchy exposed to the programming model and enabling a larger number of clusters to be employed. The coprocessor is idled during remaining portions of the program to reduce power dissipation.
Abstract:
A finger imaging system for receiving the finger of a person being fingerprinted by an automated fingerprint reader. The system includes a finger imaging device having a finger receiving portion for receiving the finger to be fingerprinted. Extending outward from the finger receiving surface is a locator bar that is located to engage a crease of the subject finger when it is in approximately the desired position. The locator bar may be fixed by or movably attached to the finger receiving surface, or may protrude through the finger receiving surface, possibly being attached to an interior movement mechanism. The locator bar may clean the finger as it is being positioned, and may include sensors for sensing non-image information to verify the legitimacy of an offered finger. The locator bar may also include a shunt for diverting unwanted static electricity stored on the finger before it is positioned for fingerprinting.