公开(公告)号：US5280233A

公开(公告)日：1994-01-18

申请号：US842294

申请日：1992-02-26

Applicant: Vanni Poletto ,  Marco Morelli ,  Bruno Murari

Inventor： Vanni Poletto ,  Marco Morelli ,  Bruno Murari

IPC: G05F1/56 ,  G05F1/569 ,  G05F1/59 ,  H02J9/06

CPC classification number: G05F1/59 ,  G05F1/569 ,  H02J9/061 ,  Y10T307/527 ,  Y10T307/625

Abstract: A voltage regulator comprising a first power switch connected between the input terminal and output terminal; a storage condenser connected to the input terminal via a one-way switch; a second power switch connected between the condenser and the input terminal; and a regulating element connected to the output terminal and driving the power switches in such a manner as to maintain the output voltage constant. For better distributing electric and thermal stress and improving the reliability and working life of the regulator by reducing the interference caused by switching of the two power switches, a drive device is provided between the regulating element and the switches for detecting the input voltage and the voltage of the condenser, and keeping both switches on as long as the input voltage is above two given thresholds, turning off the second switch when the input voltage is higher than the condenser voltage and below the first threshold, and turning off the first switch when the input voltage is lower than the condenser voltage and below the second threshold.

Abstract translation: 一种电压调节器，包括连接在输入端子和输出端子之间的第一电源开关; 存储电容器，其通过单向开关连接到所述输入端子; 连接在电容器和输入端子之间的第二电源开关; 以及连接到输出端子并且以保持输出电压恒定的方式驱动电源开关的调节元件。 为了更好地分配电力和热应力，通过减少由两个电源开关切换引起的干扰，提高了稳压器的可靠性和使用寿命，驱动装置设置在调节元件和开关之间，用于检测输入电压和电压 并且只要输入电压高于两个给定阈值就保持两个开关接通，当输入电压高于冷凝器电压并低于第一阈值时关闭第二开关，并且当第二开关断开时，关闭第一开关 输入电压低于电容电压，低于第二阈值。

公开(公告)号：US5276405A

公开(公告)日：1994-01-04

申请号：US919891

申请日：1992-07-27

Applicant: Michelangleo Mazzucco ,  Vanni Poletto ,  Marco Morelli

Inventor： Michelangleo Mazzucco ,  Vanni Poletto ,  Marco Morelli

IPC: G01N27/409 ,  H03F3/45

CPC classification number: H03F3/45479 ,  H03F3/45076 ,  H03F2200/261

Abstract: An amplifier having a high input dynamic range as well as high CMRR and PSRR values and input impedance while using a single supply voltage, includes an input stage with two transistors which are biased by a constant current, preferably of less than 1 microampere, while the collectors of the transistors are kept at fixed reference voltages. The input signal applied between the emitters of the transistors is transferred to the terminals of a first resistor which is supplied with current from a circuit which mirrors the current into a second resistor, from the terminals of which the output signal is taken.The preferred application is for forming interfaces for lambda probes fitted to catalytic converters for motor vehicles.

Abstract translation: 具有高输入动态范围的放大器以及使用单电源电压时的高CMRR和PSRR值和输入阻抗，包括具有两个晶体管的输入级，其中两个晶体管被恒定电流偏置，优选小于1微安，而 晶体管的集电极保持在固定的参考电压。 施加在晶体管的发射极之间的输入信号被传送到第一电阻器的端子，该第一电阻器从从其输出信号的端子反射电流到第二电阻器的电路提供电流。 优选的应用是形成用于机动车辆的催化转化器的λ探针的界面。

公开(公告)号：US5270590A

公开(公告)日：1993-12-14

申请号：US806118

申请日：1991-12-12

Applicant: Luigi Pascucci

Inventor： Luigi Pascucci

IPC: G11C17/00 ,  G11C7/14 ,  G11C16/06 ,  G11C16/28 ,  G11C29/00 ,  G11C29/56 ,  H03F3/45 ,  H03K5/22

CPC classification number: G11C16/28 ,  G11C7/14

Abstract: The sense circuit, for recognizing the virgin or programmed status of cells in storage devices, comprises a differential amplifier having a first input connected to a number of selectable matrix cells, through a first uncoupling circuit, a second input connected to a number of selectable reference virgin cells through a second uncoupling circuit, respective matrix and reference load transistors connected between each input of the amplifier and a supply voltage, and a current generator connected in parallel to the matrix cells and controlled by the first input of the amplifier to draw a current equal to a predetermined fraction of the current flowing through said first input.

公开(公告)号：US5267202A

公开(公告)日：1993-11-30

申请号：US725987

申请日：1991-07-05

Applicant: Marco Dallabora ,  Paolo Rolandi ,  Marco Maccalli

Inventor： Marco Dallabora ,  Paolo Rolandi ,  Marco Maccalli

IPC: G11C17/00 ,  G11C16/06 ,  G11C16/28 ,  G11C11/40

CPC classification number: G11C16/28

Abstract: The device comprises a source bias generator suitable for conferring upon the EPROM cell during the reading step a source voltage that varies linearly with the power supply voltage so as to keep constant the voltage between gate and source of the above cell.

公开(公告)号：US5231338A

公开(公告)日：1993-07-27

申请号：US613290

申请日：1990-11-15

Applicant: Olivo Bulgarelli ,  Edgardo Balboni ,  Giulia Gianoli

Inventor： Olivo Bulgarelli ,  Edgardo Balboni ,  Giulia Gianoli

IPC: H02P6/18

CPC classification number: H02P6/18

Abstract: A control circuit is used for driving a multiphase brushless DC motor. The back emf of a non-excited winding is sensed, and a control signal is generated when a sinusoidal signal on the winding crosses a reference voltage level. Commutation occurs when the control signal is generated. Masking circuitry inhibits sensing of back emf immediately after commutation for a time period which is sufficient to ensure that noise from commutation spikes has ceased.

公开(公告)号：US5231051A

公开(公告)日：1993-07-27

申请号：US769600

申请日：1991-10-01

Applicant: Livio Baldi ,  Pietro Erratico

Inventor： Livio Baldi ,  Pietro Erratico

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/768

CPC classification number: H01L21/76879 ,  H01L21/7684 ,  Y10S438/963 ,  Y10S438/976

Abstract: An improved planarity when forming contact plugs by a blanket CVD deposition of a metallic matrix layer followed by etchback is achieved by performing a first etchback step to expose the surface of the dielectric material underlying the filling metal layer, while masking the top of the metal plugs with resist caps. The resist caps are formed using a mask derived by field inversion and enlargement from the actual contact mask used for defining the contact areas. With the resist caps covering the contact plugs, the filling metallic material is overetched to eliminate residues along with discontinuities from the planarity of the surface, while shielding the top of the plugs from the overetch. The masked overetch is preferably conducted under conditions of reduced anisotropy and increased selectivity in respect to the first etchback step.

公开(公告)号：US5196914A

公开(公告)日：1993-03-23

申请号：US753028

申请日：1991-08-29

Applicant: Stefano Mazzali

Inventor： Stefano Mazzali

IPC: G11C16/04 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788

CPC classification number: H01L27/115 ,  G11C16/0416 ,  H01L29/42376 ,  H01L29/7885

Abstract: A table cloth matrix of EPROM memory cells comprises a semiconductor substrate, parallel source lines and drain lines, floating gate areas interposed in a checkerboard pattern between the source lines and the drain lines and control gate lines, parallel to one another and perpendicular to the source lines and to the drain lines. There are obtained in the semiconductor substrate extensive oxide areas, with which the floating gates are in contact by means of their asymmetrical lateral fin.

Abstract translation: EPROM存储单元的桌布矩阵包括半导体衬底，平行的源极线和漏极线，在源极线和漏极线之间的棋盘图案中插入的浮动栅极区域和控制栅极线彼此平行并垂直于源极 线路和排水管线。 在半导体衬底中获得了大量的氧化物区域，浮动栅极通过它们的非对称横向翅片与之接触。

公开(公告)号：US5140591A

公开(公告)日：1992-08-18

申请号：US446866

申请日：1989-12-06

Applicant: Sergio Palara ,  Paolo Monaco

Inventor： Sergio Palara ,  Paolo Monaco

IPC: H02P7/288 ,  H02M7/538 ,  H02P7/00 ,  H03K4/94 ,  H03K17/0812 ,  H03K17/16 ,  H03K17/687

CPC classification number: H03K17/6871 ,  H02M7/538 ,  H02P7/04 ,  H03K17/08122 ,  H03K4/94

Abstract: The generator of drive signals comprises a ramp generator suitable for receiving a square waveform input signal and for converting it into an output signal variable between a lower level and an upper level with upward and downward ramps having a preset slope, a first comparator with a non-inverting input connected to the output of said ramp generator and an inverting input connected to a first reference signal source and a second comparator with an inverting input connected to the output of said ramp generator and a non-inverting input connected to a second reference signal source.

公开(公告)号：US5140185A

公开(公告)日：1992-08-18

申请号：US436777

申请日：1989-11-15

Applicant: Loic Lietar

Inventor： Loic Lietar

IPC: G01R19/00 ,  G01R19/165 ,  H03K5/24

CPC classification number: H03K5/2418 ,  G01R19/1658

Abstract: The level detector comprises a first capacitance having a charge circuit including a first transistor controlled by the input signal to be detected (Vi) and a discharge circuit. A second capacitance has a charge circuit including a second transistor controlled by the input signal and a discharge circuit having at least one third transistor having pre-set electrical and geometrical characteristics. The above discharge circuits are connected to the respective inputs of a comparator whose output is representative of the difference between the maximum amplitude of the input signal and a reference level depending on said electrical and geometrical characteristics of said third transistor.

公开(公告)号：US5136258A

公开(公告)日：1992-08-04

申请号：US768457

申请日：1991-09-30

Applicant: Germano Nicollini ,  Rinaldo Castello

Inventor： Germano Nicollini ,  Rinaldo Castello

IPC: H03F3/45

CPC classification number: H03F3/45179 ,  H03F3/45076 ,  H03F3/45183 ,  H03F2203/45026 ,  H03F2203/45036 ,  H03F2203/45192 ,  H03F2203/45251 ,  H03F2203/45288 ,  H03F2203/45318 ,  H03F2203/45658

Abstract: A circuit arrangement for enhancing the transconductance of a differential amplifier stage comprising a pair of MOS transistors, having respective source electrodes connected together through a circuit node, comprises a pair of active components respectively connected in each of the connections between the aforesaid electrodes and the aforesaid node and serving a characteristic function corresponding to that of a negative value resistor. This arrangement enables the transconductance of the differential stage to be increased while keeping the dissipated electric power low and the area occupied in an integrated circuit small.

Abstract translation: 一种用于增强包括一对MOS晶体管的差分放大器级的跨导的电路装置，其具有通过电路节点连接在一起的各个源极，包括分别连接在上述电极和上述电极之间的每个连接中的一对有源元件 并提供与负值电阻器相对应的特征函数。 这种布置使得能够增加差分级的跨导，同时保持耗散的功率低并且集成电路中占据的面积小。