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公开(公告)号：US11817034B2
公开(公告)日：2023-11-14
申请号：US17044190
申请日：2019-12-20
Inventor： Xuehuan Feng , Yongqian Li , Dacheng Zhang , Lang Liu
CPC classification number: G09G3/2092 , H01L27/1251 , H01L27/1255 , G09G2300/0842 , G09G2310/0267
Abstract: A display substrate includes: a base substrate; a first conductive pattern arranged on the base substrate; a first insulation layer arranged at a side of the first conductive pattern away from the base substrate; a second conductive pattern arranged at a side of the first insulation layer away from the base substrate; a second insulation layer arranged at a side of the second conductive pattern away from the base substrate; and a third conductive pattern arranged at a side of the second insulation layer away from the base substrate. The third conductive pattern and the first conductive pattern together serve as a first electrode plate of the capacitor, and the second conductive pattern serves as a second electrode plate of the capacitor.
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332.发明授权公开(公告)号：US11817028B2
公开(公告)日：2023-11-14
申请号：US18077269
申请日：2022-12-08
Inventor： Xuehuan Feng , Pan Xu
CPC classification number: G09G3/20 , G11C19/28 , G09G2300/0426 , G09G2310/0267 , G09G2310/0286 , G09G2310/08 , H01L27/124 , H01L27/1255
Abstract: The present disclosure relates to the field of display technology, and in particular, to a gate driving structure, an array substrate and a display device. The gate driving structure may include: a base substrate; a shift register, formed on the base substrate, and including a plurality of thin film transistors and at least one capacitor, the capacitor being coupled to the thin film transistor; and a signal wiring group, formed on the base substrate, and including a plurality of signal wirings spaced apart from each other, the signal wiring being coupled to the thin film transistor. An orthographic projection of the capacitor on the base substrate is at least partially overlapped with an orthographic projection of the signal wiring group on the base substrate.
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333.发明公开公开(公告)号：US20230306924A1
公开(公告)日：2023-09-28
申请号：US17776267
申请日：2020-11-24
Inventor： Xuehuan FENG , Yongqian LI
CPC classification number: G09G3/3677 , G09G3/2092 , G09G2310/0286 , G09G2310/08
Abstract: A shift register circuit includes an input sub-circuit, an output sub-circuit and a control sub-circuit. The input sub-circuit is coupled to a first input signal terminal and a pull-up node, and configured to, under control of a first input signal, transmit the first input signal to the pull-up node. The output sub-circuit is at least coupled to the pull-up node, a first clock signal terminal and a first signal output terminal, and configured to transmit a first clock signal to the first signal output terminal under control of a voltage at the pull-up node. The control sub-circuit is coupled to at least one first reference node, at least one first control signal terminal and the pull-up node, and configured to transmit a voltage at a first reference node to the pull-up node under control of a first control signal.
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公开(公告)号：US20230306892A1
公开(公告)日：2023-09-28
申请号：US18325140
申请日：2023-05-30
Inventor： Xuehuan Feng , Yongqian Li , Xing Zhang
IPC: G09G3/20
CPC classification number: G09G3/2092 , G09G2310/0286 , G09G2310/061 , G09G2310/08
Abstract: A shift-register unit includes a first circuit including a first input circuit coupled via a first node to a first output circuit, and a second circuit including a second input circuit coupled via a second node to a second output circuit. The first input circuit is configured to control a voltage level of the first node in response to a first input signal. The first output circuit is configured to output a shift-register signal and a first output signal in response to the voltage level of the first node. The second input circuit is configured to control a voltage level of the second node in response to the first input signal. The second output circuit is configured to output a second output signal in response to the voltage level of the second node. The first input circuit and the second input circuit have a same circuit structure.
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公开(公告)号：US20230274695A1
公开(公告)日：2023-08-31
申请号：US18313457
申请日：2023-05-08
Inventor： Song MENG , Xuehuan Feng
IPC: G09G3/3225
CPC classification number: G09G3/3225 , G09G2300/0819 , G09G2310/08
Abstract: The present disclosure relates to the field of display technology, and describes a pixel driving circuit detection method, a display panel, a driving method thereof, and a display device. The detection method includes inputting a reference voltage to the data line during at least part of the initial phase; turning on the first and second switch sub-circuits during the charging phase, to input the detection voltage to the data line, while inputting the reset voltage to the sensing line; turning on the second switch sub-circuit during the charging phase, to input the driving current by the driving transistor to the sensing line under the effect of the detection voltage; turning off the first and second switch sub-circuits during the detection phase, to detect the voltage on the sensing line; and obtaining the mobility of the driving transistor according to the voltage on the sensing line detected in the detection phase.
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Patent Agency Ranking
336.发明授权公开(公告)号：US11735119B2
公开(公告)日：2023-08-22
申请号：US17750804
申请日：2022-05-23
Inventor： Zhidong Yuan , Yongqian Li , Can Yuan
IPC: G09G3/32 , G09G3/3266 , G11C19/28 , G09G3/3233
CPC classification number: G09G3/3266 , G11C19/28 , G09G3/3233 , G09G2310/0286 , G09G2310/061 , G09G2310/08
Abstract: A shift register unit and a control method thereof, a gate driving circuit and a control method thereof, and a display apparatus are provided. The shift register unit includes: a first shift register coupled to an input signal terminal, a first clock signal terminal and a second clock signal terminal. The first shift register is configured to generate a first output signal based on the signal at the first clock signal terminal and generate a second output signal based on the signal at the second clock signal terminal; and a second shift register coupled to the input signal terminal and a third clock signal terminal, the second shift register is configured to generate a third output signal based on the signal at the third clock signal terminal. The first shift register includes a first control circuit, a first output circuit and a second output circuit.
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公开(公告)号：US11705047B2
公开(公告)日：2023-07-18
申请号：US17721234
申请日：2022-04-14
Inventor： Xuehuan Feng , Yongqian Li , Xing Zhang
IPC: G09G3/20
CPC classification number: G09G3/2092 , G09G2310/0286 , G09G2310/061 , G09G2310/08
Abstract: A shift-register unit includes a first circuit including a first input circuit coupled via a first node to a first output circuit, and a second circuit including a second input circuit coupled via a second node to a second output circuit. The first input circuit is configured to control a voltage level of the first node in response to a first input signal. The first output circuit is configured to output a shift-register signal and a first output signal in response to the voltage level of the first node. The second input circuit is configured to control a voltage level of the second node in response to the first input signal. The second output circuit is configured to output a second output signal in response to the voltage level of the second node. The first input circuit and the second input circuit have a same circuit structure.
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公开(公告)号：US11699382B2
公开(公告)日：2023-07-11
申请号：US17780626
申请日：2021-07-21
Inventor： Xuehuan Feng , Xing Yao , Jingbo Xu , Xuelian Cheng
IPC: G09G3/3266 , G09G3/20
CPC classification number: G09G3/2074 , G09G3/3266 , G09G2300/0443 , G09G2310/061 , G09G2310/08 , G09G2320/0257
Abstract: Provided is a method for driving a display device including n rows of sub-pixels; the method includes: driving the first frame of image, including: performing normal display driving on the n rows of sub-pixels in a display driving period, performing darkness insertion driving on a rows, from the 1st to ath rows, of sub-pixels in a first darkness insertion sub-period, and performing darkness insertion driving on (n−a) rows, from the (a+1)th to nth rows, of sub-pixels in a second darkness insertion sub-period driving a second frame of image, including: performing normal display driving on the n rows of sub-pixels in a display driving period, performing darkness insertion driving on b rows, from the 1st to bth rows, of sub-pixels in a first darkness insertion sub-period, and performing darkness insertion driving on (n−b) rows, from the (b+1)th to nth rows, of sub-pixels in a second darkness insertion sub-period.
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公开(公告)号：US20230196994A1
公开(公告)日：2023-06-22
申请号：US18108730
申请日：2023-02-13
Inventor： Xuehuan FENG , Yongqian LI , Hao LIU
IPC: G09G3/3225 , G11C19/28 , G09G3/3266
CPC classification number: G09G3/3225 , G11C19/28 , G09G3/3266 , G09G2310/0286
Abstract: A shift register unit, a gate driving circuit, a display device, and a driving method are disclosed. The shift register unit includes a first sub-circuit, a second sub-circuit, a leakage prevention circuit and a blanking input sub-circuit, wherein the first sub-circuit comprises a first input circuit and a first output circuit; the second sub-circuit comprises a second input circuit and a second output circuit; the leakage prevention circuit is configured to control a level of a leakage prevention node under control of the level of the first node, so as to turn off a circuit connected between the first node and the leakage prevention node; and the blanking input sub-circuit is connected to the first node and the second node, and is configured to receive a selection control signal and a first clock signal, and control the level of the first node and the level of the second node.
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公开(公告)号：US20230157111A1
公开(公告)日：2023-05-18
申请号：US17795950
申请日：2021-09-28
Inventor： Pan Xu , Zhidong Yuan
IPC: H10K59/131 , G09G3/3233 , H10K59/122
CPC classification number: H10K59/1315 , G09G3/3233 , H10K59/122 , G09G2300/0842 , G09G2300/0819 , G09G2300/0426
Abstract: A display substrate is provided. The display substrate includes: a base substrate including a display area and a peripheral area located on at least a first side of the display area; a plurality of pixel units arranged in an array along a first direction and a second direction in the display area of the base substrate, where the pixel units include a pixel driver circuit and a light-emitting device electrically connected to the pixel driver circuit, and the light-emitting device includes a cathode, an anode, and a light-emitting layer disposed between the cathode and the anode; and a cathode line located in the peripheral area and electrically connected to the cathode. The cathode line substantially surrounds the display area and is electrically connected to the cathode line at a plurality of positions. The cathode line includes a first cathode sub-line located in the same layer as the anode.
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