公开(公告)号：US07076012B2

公开(公告)日：2006-07-11

申请号：US10230733

申请日：2002-08-29

Applicant: Ross E. Dermott ,  Tyler J. Gomm

Inventor： Ross E. Dermott ,  Tyler J. Gomm

IPC: H04L7/00 ,  H04L7/02

CPC classification number: G06F1/12

Abstract: A timing control circuit for synchronizing an output clock signal with an input clock signal includes a pulse generator, a measure delay array, a measure circuit, and a forward delay array. The pulse generator is configured to receive a delay clock signal generated based on the input clock signal and generate a pulse, the pulse having a falling edge corresponding to a rising edge of the delay clock signal. The measure delay array is coupled to the pulse generator to receive the pulse. The measure circuit is configured to determine a position of the pulse within the measure delay array corresponding to a rising edge of the input clock signal. The forward delay array is configured to receive the input clock signal and delay the input clock signal based on the position determined by the measure circuit to generate the output clock signal. A method for synchronizing an output clock signal with an input clock signal includes receiving a delay clock signal generated based on the input clock signal. A pulse is generated having a falling edge corresponding to a rising edge of the delay clock signal. The pulse is propagated through a measure delay array. A position of the pulse within the measure delay array corresponding to a rising edge of the input clock signal is determined. The input clock signal is delayed based on the position determined by the measure circuit to generate the output clock signal.

Abstract translation: 用于使输出时钟信号与输入时钟信号同步的定时控制电路包括脉冲发生器，测量延迟阵列，测量电路和前向延迟阵列。 脉冲发生器被配置为接收基于输入时钟信号产生的延迟时钟信号并产生脉冲，该脉冲具有对应于延迟时钟信号的上升沿的下降沿。 测量延迟阵列耦合到脉冲发生器以接收脉冲。 测量电路被配置为确定与输入时钟信号的上升沿对应的测量延迟阵列内的脉冲的位置。 正向延迟阵列被配置为接收输入时钟信号并且基于由测量电路确定的位置来延迟输入时钟信号以产生输出时钟信号。 一种使输出时钟信号与输入时钟信号同步的方法包括接收基于输入时钟信号产生的延迟时钟信号。 产生具有对应于延迟时钟信号的上升沿的下降沿的脉冲。 脉冲通过测量延迟阵列传播。 确定与输入时钟信号的上升沿对应的测量延迟阵列内的脉冲的位置。 输入时钟信号基于由测量电路确定的位置而被延迟以产生输出时钟信号。

公开(公告)号：US06975556B2

公开(公告)日：2005-12-13

申请号：US10684123

申请日：2003-10-09

Applicant: Aaron M. Schoenfeld ,  Ross E. Dermott

Inventor： Aaron M. Schoenfeld ,  Ross E. Dermott

IPC: G11C7/22 ,  G11C11/406 ,  G11C8/00

CPC classification number: G11C7/222 ,  G11C7/22 ,  G11C11/406 ,  G11C2211/4061 ,  G11C2211/4067

Abstract: A method and apparatus is provided for idling a clock synchronizing circuit during at least a portion of time during execution of a refresh operation in a memory device. In a memory device receiving an external clock signal, a method and apparatus for executing a refresh operation is provided that includes initiating at least one refresh operation in the memory device, and ceasing generation of an internal clock signal timed with respect to the external clock signal for at least a portion of the time in which at least one refresh operation takes to complete.

Abstract translation: 提供一种方法和装置，用于在执行存储器件中的刷新操作期间的至少一部分时间内使时钟同步电路空转。 在接收外部时钟信号的存储器件中，提供一种用于执行刷新操作的方法和装置，其包括启动存储器件中的至少一个刷新操作，并停止产生相对于外部时钟信号定时的内部时钟信号 对于至少一次刷新操作需要完成的时间的至少一部分。

公开(公告)号：US06864702B1

公开(公告)日：2005-03-08

申请号：US10746984

申请日：2003-12-24

Applicant: Ross E. Teggatz ,  Reed W. Adams ,  Suribhotla V. Rajasekhar

Inventor： Ross E. Teggatz ,  Reed W. Adams ,  Suribhotla V. Rajasekhar

IPC: G01R31/28 ,  G01R31/27

CPC classification number: G01R31/2858

Abstract: The present invention provides a system for stress testing an oxide structure to determine that structure's reliability in overstress conditions. The present invention provides an overstress test structure (400) that comprises a first transistor (406), having a first terminal coupled to ground, a second terminal coupled to a control signal (402), and a third terminal coupled to a first end of a first resistive element (412). A first voltage source (414) is coupled to the second end of the first resistive element. A second resistive element (416) is intercoupled between the second end of the first resistive element and ground. A second transistor (418) has a first terminal coupled to the second end of the first resistive element, a second terminal coupled to the first end of the first resistive element, and a third terminal coupled to a first node (420). A third resistive element (422) is intercoupled between the third terminal of the second transistor and ground; and a third transistor (424) has a first terminal coupled (426) to the oxide structure, a second terminal coupled to the first end of the first resistive elerment, and a third terminal coupled to a second voltage source (428).

Abstract translation: 本发明提供了一种用于对氧化物结构进行应力测试以确定该结构在过应力条件下的可靠性的系统。 本发明提供了一种过应力测试结构（400），其包括第一晶体管（406），其具有耦合到地的第一端子，耦合到控制信号（402）的第二端子和耦合到控制信号 第一电阻元件（412）。 第一电压源（414）耦合到第一电阻元件的第二端。 第二电阻元件（416）在第一电阻元件的第二端和地之间相互配合。 第二晶体管（418）具有耦合到第一电阻元件的第二端的第一端子，耦合到第一电阻元件的第一端的第二端子和耦合到第一节点（420）的第三端子。 第三电阻元件（422）在第二晶体管的第三端与地之间相互耦合; 和第三晶体管（424）具有耦合到所述氧化物结构的第一端子（426），耦合到所述第一电阻器的第一端的第二端子和耦合到第二电压源（428）的第三端子。

公开(公告)号：US06852754B1

公开(公告)日：2005-02-08

申请号：US10763993

申请日：2004-01-22

Applicant: Amy E. Wright ,  Ross E. Longley ,  Srinivasa Reddy Natala ,  John K. Reed

Inventor： Amy E. Wright ,  Ross E. Longley ,  Srinivasa Reddy Natala ,  John K. Reed

IPC: C07D307/00 ,  A61K31/35 ,  C07D307/92

CPC classification number: C07D307/00

Abstract: The subject invention provides novel compositions of biologically active linderazulene terpene compounds which can advantageously be used for treating cancer and stopping cell proliferation.

Abstract translation: 本发明提供了可以有利地用于治疗癌症和阻止细胞增殖的生物活性粘多菌萜烯化合物的新组合物。

公开(公告)号：US06835736B1

公开(公告)日：2004-12-28

申请号：US10376118

申请日：2003-02-28

Applicant: Sarath P. Gunasekera ,  Ross E. Longley ,  Shirley A. Pomponi ,  Amy E. Wright

Inventor： Sarath P. Gunasekera ,  Ross E. Longley ,  Shirley A. Pomponi ,  Amy E. Wright

IPC: A61K3144

CPC classification number: C07D471/10 ,  A61K31/44

Abstract: The subject invention provides novel compositions of biologically active discorhabdin compounds which can advantageously be used for inhibiting pathological cellular proliferation. The compounds of the subject invention have utility for use in the treatment of cancer, including tumors.

Abstract translation: 本发明提供了可以有利地用于抑制病理性细胞增殖的生物活性的discorhabdin化合物的新组合物。 本发明的化合物可用于治疗包括肿瘤在内的癌症。

公开(公告)号：US06784160B1

公开(公告)日：2004-08-31

申请号：US10410335

申请日：2003-04-09

Applicant: Amy E. Wright ,  John K. Reed ,  Ross E. Longley

Inventor： Amy E. Wright ,  John K. Reed ,  Ross E. Longley

IPC: A61K3170

CPC classification number: C07H3/00

Abstract: The subject invention provides novel compositions of biologically active glycosylated pregnene compounds which can advantageously be used for treating cancer and stopping cell proliferation.

Abstract translation: 本发明提供了可有利地用于治疗癌症和阻止细胞增殖的生物活性糖基化孕烯化合物的新组合物。

公开(公告)号：US06781861B2

公开(公告)日：2004-08-24

申请号：US10424508

申请日：2003-04-28

Applicant: Tyler J. Gomm ,  Aaron M. Schoenfeld ,  Travis E. Dirkes ,  Ross E. Dermott

Inventor： Tyler J. Gomm ,  Aaron M. Schoenfeld ,  Travis E. Dirkes ,  Ross E. Dermott

IPC: G11C700

CPC classification number: G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C2207/2254

Abstract: A method and apparatus to characterize a synchronous device after it is packaged. For synchronous devices, such as SDRAMs implementing a Delay Locked Loop (DLL) to synchronize one signal, such as an external clock signal with a second signal, such as a data signal, a counter is coupled to the phase detector of the DLL to track the entry point of the delay line. The entry point information can be taken over a variety of voltages, temperatures, and frequencies to characterize the DLL. The counter may be located on the synchronous device or external to the device.

Abstract translation: 在同步装置封装之后对其进行表征的方法和装置。 对于同步装置，例如实现延迟锁定环（DLL）以同步一个信号的SDRAM（例如具有诸如数据信号的第二信号的外部时钟信号）计数器的SDRAM被耦合到DLL的相位检测器以跟踪 延迟线的入口点。 入口点信息可以通过各种电压，温度和频率来表征DLL。 计数器可能位于同步设备上或设备外部。

公开(公告)号：US06737897B2

公开(公告)日：2004-05-18

申请号：US10231509

申请日：2002-08-29

Applicant: Tyler J. Gomm ,  Travis E. Dirkes ,  Ross E. Dermott ,  Daniel R. Loughmiller ,  Scott E. Smith

Inventor： Tyler J. Gomm ,  Travis E. Dirkes ,  Ross E. Dermott ,  Daniel R. Loughmiller ,  Scott E. Smith

IPC: H03D324

CPC classification number: G11C7/02 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0802 ,  H03L7/0814 ,  H03L7/089

Abstract: A delay locked loop circuit includes a plurality of delay cells connected in series. Each of the delay cells connects to an input node which provides a clock signal. A shift register selects one of the delay cells to allow the clock signal to enter the selected delay cell and propagate to an output node, such that internal gates of delay cells preceding the selected delay cell are not toggling.

Abstract translation: 延迟锁定环电路包括串联连接的多个延迟单元。 每个延迟单元连接到提供时钟信号的输入节点。 移位寄存器选择一个延迟单元以允许时钟信号进入所选择的延迟单元并传播到输出节点，使得在所选延迟单元之前的延迟单元的内部门不切换。

公开(公告)号：US06696861B1

公开(公告)日：2004-02-24

申请号：US10285900

申请日：2002-11-01

Applicant: David J. Baldwin ,  Zbigniew J. Lata ,  Sanmukh M. Patel ,  Ross E. Teggatz

Inventor： David J. Baldwin ,  Zbigniew J. Lata ,  Sanmukh M. Patel ,  Ross E. Teggatz

IPC: H03K1716

CPC classification number: H02M3/156 ,  H02M3/1563 ,  H02M3/1588 ,  Y02B70/1466

Abstract: A switch mode controller circuit includes: a hysteretic comparator HYST_COMP for monitoring an output of a switch mode circuit; a standard comparator PHASE_COMP for monitoring a phase of the switch mode circuit; a logic block having a first input coupled to a clock signal generator Oscillator, a second input coupled to an output of the hysteretic comparator HYST_COMP, and a third input coupled to an output of the standard comparator PHASE_COMP, wherein the logic block generates switching cycles based on a fixed ON/OFF time during a first part of a cycle and based on a hysteretic control during a second part of the cycle.

Abstract translation: 开关模式控制器电路包括：用于监视开关模式电路的输出的滞后比较器HYST_COMP; 用于监视开关模式电路的相位的标准比较器PHASE_COMP; 逻辑块，其具有耦合到时钟信号发生器振荡器的第一输入，耦合到迟滞比较器HYST_COMP的输出的第二输入和耦合到标准比较器PHASE_COMP的输出的第三输入，其中逻辑块基于 在循环的第一部分期间处于固定的ON / OFF时间，并且基于在循环的第二部分期间的滞后控制。

公开(公告)号：US06674621B2

公开(公告)日：2004-01-06

申请号：US09989066

申请日：2001-11-21

Applicant: Alexander Noam Teutsch ,  Zbigniew Jan Lata ,  David John Baldwin ,  Ross E. Teggatz

Inventor： Alexander Noam Teutsch ,  Zbigniew Jan Lata ,  David John Baldwin ,  Ross E. Teggatz

IPC: F21V704

CPC classification number: H01L27/0255 ,  H02H11/003

Abstract: The present invention relates to a reverse bias protection structure which comprises a PMOS transistor structure having a drain portion, a gate portion, a source portion and a backgate portion, wherein the gate portion is coupled to a first voltage potential, the source portion is selectively coupleable to a power supply, and the drain portion is selectively coupleable to a circuit needing power to be supplied thereto from the power supply. The reverse bias protection structure further comprises a Schottky diode structure having an anode coupled to the source portion of the PMOS transistor structure, and a cathode coupled to the backgate portion of the PMOS structure. Under forward bias conditions, the PMOS transistor conducts and exhibits a small voltage drop thereacross. Under reverse bias conditions, the PMOS transistor is off and the Schottky structure is reverse biased, thus preventing current through the protection structure.

Abstract translation: 本发明涉及一种反偏置保护结构，其包括具有漏极部分，栅极部分，源极部分和后栅极部分的PMOS晶体管结构，其中栅极部分耦合到第一电压电位，源极部分选择性地 可与电源连接，并且漏极部分选择性地耦合到需要从电源供给的电力的电路。 反向偏置保护结构还包括具有耦合到PMOS晶体管结构的源极部分的阳极的肖特基二极管结构以及耦合到PMOS结构的背栅极部分的阴极。 在正向偏置条件下，PMOS晶体管导通并呈现出小的电压降。 在反向偏置条件下，PMOS晶体管截止，肖特基结构反向偏置，从而防止电流通过保护结构。