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31.发明授权Data processing apparatus and method for moving data elements between specified registers and a continuous block of memory 有权用于在指定的寄存器和连续的存储器块之间移动数据元素的数据处理装置和方法公开(公告)号：US07219215B2
公开(公告)日：2007-05-15
申请号：US10889367
申请日：2004-07-13
申请人： Simon Andrew Ford , Dominic Hugo Symes , Andrew Christopher Rose , David Raymond Lutz , Christopher Neal Hinds
发明人： Simon Andrew Ford , Dominic Hugo Symes , Andrew Christopher Rose , David Raymond Lutz , Christopher Neal Hinds
IPC分类号： G06F9/40
CPC分类号： G06F9/30167 , G06F9/30025 , G06F9/30036 , G06F9/3004 , G06F9/30145
摘要： A data processing apparatus and method are provided for moving data between registers and memory. The data processing apparatus comprises a register data store having a plurality of registers operable to store data elements. A processor is operable to perform in parallel a data processing operation on multiple data elements accessed in at least one of the registers. Access logic is operable in response to a single access instruction to move a plurality of data elements between specified registers and a continuous block of memory in which data elements are stored as an array of structures having a structure format, the structure format having a plurality of components. The single access instruction identifies the number of components in the structure format, and the access logic is further operable to rearrange the plurality of data elements as they are moved such that each specified register stores data elements of one component whilst in memory the data elements are stored as the array of structures.
摘要翻译： 提供了一种用于在寄存器和存储器之间移动数据的数据处理装置和方法。 数据处理装置包括具有可操作以存储数据元素的多个寄存器的寄存器数据存储器。 处理器可操作以对在至少一个寄存器中访问的多个数据元素并行地执行数据处理操作。 访问逻辑可操作以响应于单个访问指令来移动指定寄存器之间的多个数据元素和其中数据元素被存储为具有结构格式的结构的阵列的连续存储块，所述结构格式具有多个 组件。 单个访问指令标识结构格式的组件的数量，并且访问逻辑还可用于在移动多个数据元素时重新排列多个数据元素，使得每个指定的寄存器存储一个组件的数据元素，而在存储器中数据元素是 存储为结构数组。
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32.发明授权Write-through caching a JAVA® local variable within a register of a register bank 有权直写缓存在注册库的寄存器中的JAVA（R）局部变量公开(公告)号：US07131118B2
公开(公告)日：2006-10-31
申请号：US10201956
申请日：2002-07-25
CPC分类号： G06F8/4441
摘要： In a data processing apparatus 2 having a first mode of operation in which JAVA® bytecodes 46, 48 specify the processing operations and a second mode of operation in which other instructions specify the processing operations. In order to speed operation, the JAVA® Local Variable 0, or another such variable, is stored within a register of a register bank 14 to be available for rapid access. This storage is in a write-through manner such that reads of the value will be directly serviced from the register R4 and writes to the data value will be made in both the register R4 and back in the original memory location for that data value as determined by the JAVA® Virtual Machine.
摘要翻译： 在具有JAVA（R）字节码46,48指定处理操作的第一操作模式的数据处理设备2和其他指令指定处理操作的第二操作模式。 为了加速操作，JAVA（局部变量0）或另一个这样的变量被存储在寄存器组14的寄存器内以便可用于快速访问。 该存储器是以直写方式进行的，使得该值的读取将从寄存器R 4直接服务，并且写入数据值将在寄存器R 4中和在该数据值的原始存储器位置中进行 由JAVA虚拟机确定。
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公开(公告)号：US07089539B2
公开(公告)日：2006-08-08
申请号：US10081215
申请日：2002-02-25
CPC分类号： G06F9/45504
摘要： Program instructions in the form of Java bytecodes may be subject to fixed mappings to processing operations or programmable mappings to processing operations. A system is provided with a fixed mapping hardware interpreter, a programmable mapping hardware interpreter and a software interpreter. The fixed mapping hardware interpreter is able to provide high speed interpretation of the common and simple bytecodes. The programmable mapping hardware interpreter is able to provide high speed interpretation of the simple and performance critical programmable bytecodes with the remaining bytecodes and more complicated bytecodes being handled by the software interpreter.
摘要翻译： 以Java字节码形式的程序指令可能会对处理操作或可编程映射进行固定映射以进行处理操作。 系统提供有固定映射硬件解释器，可编程映射硬件解释器和软件解释器。 固定映射硬件解释器能够提供常用和简单字节码的高速解释。 可编程映射硬件解释器能够提供简单和性能关键的可编程字节码的高速解释，其余的字节码和更复杂的字节码由软件解释器处理。
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34.发明授权Decoder for generating N output signals from two or more precharged input signals 失效用于从两个或多个预充电输入信号产生N个输出信号的解码器公开(公告)号：US06172530B2
公开(公告)日：2001-01-09
申请号：US09335696
申请日：1999-06-18
IPC分类号： G11C800
CPC分类号： G11C8/00
摘要： A decoder is provided for generating N output signals, the decoder comprising a precharged gate structure arranged to receive two or more input signals and to generate N intermediate signals. In a precharge phase, the precharged gate structure is arranged to output the N intermediate signals at a first logic value, and in an evaluate phase the precharged gate structure is arranged to maintain a first intermediate signal at the first logic value, and to cause all other intermediate signals to transition to a second logic value. Further, self-timed logic is provided for receiving the N intermediate signals, and for generating the N output signals, the self-timed logic being arranged, during the precharge phase, to generate the N output signals at the second logic value, and during the evaluate phase to cause a first output signal corresponding to the first intermediate signal to transition to the first logic value. The self-timed logic is further arranged to generate each output signal from the corresponding intermediate signal as qualified to predetermined other intermediate signal, such that the transition of the first output signal to the first logic value is delayed by a first predetermined time after the predetermined other intermediate signal has transitioned to the second logic value.
摘要翻译： 提供了用于产生N个输出信号的解码器，该解码器包括预充电栅极结构，其被布置为接收两个或更多个输入信号并产生N个中间信号。 在预充电阶段，预充电栅极结构被布置为以第一逻辑值输出N个中间信号，并且在评估阶段中，预充电栅结构被布置成将第一中间信号保持在第一逻辑值，并且使所有 其他中间信号转换到第二逻辑值。 此外，提供自定时逻辑用于接收N个中间信号，并且为了产生N个输出信号，在预充电阶段期间，自定时逻辑被布置为以第二逻辑值生成N个输出信号，并且在 所述评估阶段使得对应于所述第一中间信号的第一输出信号转变到所述第一逻辑值。 自定时逻辑还被布置为从对应的中间信号产生符合预定的其他中间信号的每个输出信号，使得第一输出信号到第一逻辑值的转变在预定的第一预定时间后延迟第一预定时间 其他中间信号已经转换到第二逻辑值。
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公开(公告)号：US09288258B2
公开(公告)日：2016-03-15
申请号：US13825190
申请日：2011-10-11
IPC分类号： H04L29/08 , H04L12/40 , H04L12/46 , G06F15/78 , H04L12/701
CPC分类号： H04L67/10 , G06F15/7825 , G06F15/7842 , H04L12/40084 , H04L12/46 , H04L45/00
摘要： An integrated circuit comprising multiple master units and multiple slave units connected via interconnect circuitry utilizes token based node-to-node communication flow management within the interconnect circuitry with a network node requesting a token and receiving a token signal before it asserts its communication signals onto a physical communication link shared between multiple virtual networks.
摘要翻译： 包括通过互连电路连接的多个主单元和多个从单元的集成电路在互连电路内使用基于令牌的节点到节点通信流管理，网络节点请求令牌，并在将其通信信号置于 物理通信链路在多个虚拟网络之间共享。
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公开(公告)号：US20130219004A1
公开(公告)日：2013-08-22
申请号：US13825190
申请日：2011-10-11
IPC分类号： H04L29/08
CPC分类号： H04L67/10 , G06F15/7825 , G06F15/7842 , H04L12/40084 , H04L12/46 , H04L45/00
摘要： An integrated circuit comprising multiple master units (4, 6) and multiple slave units (10, 12) connected via interconnect circuitry (8) utilises token based node-to-node communication flow management within the interconnect circuitry (8) with a network node requesting a token and receiving a token signal before it asserts its communication signals onto a physical communication link shared between multiple virtual networks.
摘要翻译： 包括通过互连电路（8）连接的多个主单元（4,6）和多个从单元（10,12）的集成电路利用网络节点在互连电路（8）内的基于令牌的节点到节点通信流管理 在将其通信信号置于多个虚拟网络之间共享的物理通信链路之前，请求令牌并接收令牌信号。
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公开(公告)号：US20130117511A1
公开(公告)日：2013-05-09
申请号：US13291229
申请日：2011-11-08
IPC分类号： G06F12/08
CPC分类号： G06F1/3275 , G06F12/0831 , G06F2212/1008 , G06F2212/1028 , Y02D10/13 , Y02D10/14
摘要： A data processing apparatus has a cache having a normal mode and a retention mode in which the cache consumes less power than in the normal mode. An interconnect receives, from at least one other device, coherency access requests for data stored in the cache. In the normal mode, the data in the cache is accessible and the cache generates coherency responses in response to the coherency access requests, while in the retention mode the data is retained in the cache but inaccessible in response to the coherency access requests. A coherency controller is provided to monitor the coherency access requests and coherency responses. Switching of the cache from the normal mode to the retention mode is deferred until the coherency controller has detected coherency responses for all coherency access requests passed to said cache.
摘要翻译： 数据处理装置具有高速缓存，其具有正常模式和保持模式，其中高速缓存比正常模式消耗更少的功率。 互连从至少一个其他设备接收存储在高速缓存中的数据的一致性访问请求。 在正常模式下，高速缓存中的数据是可访问的，并且缓存响应于一致性访问请求而产生一致性响应，而在保持模式中，数据被保留在高速缓存中，但是响应于一致性访问请求而不可访问。 提供一致性控制器来监视一致性访问请求和一致性响应。 将缓存从正常模式切换到保留模式将延迟，直到相关性控制器检测到传递给所述高速缓存的所有一致性访问请求的一致性响应。
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公开(公告)号：US20130070879A1
公开(公告)日：2013-03-21
申请号：US13348862
申请日：2012-01-12
申请人： John Michael HORLEY , Sheldon James WOODHOUSE , Michael John WILLIAMS , Sheshadri KALKUNTE , Andrew Christopher ROSE
发明人： John Michael HORLEY , Sheldon James WOODHOUSE , Michael John WILLIAMS , Sheshadri KALKUNTE , Andrew Christopher ROSE
IPC分类号： H04L7/00
摘要： A count value generator includes an input for receiving a synchronising count value, a counter configured to increment at a local frequency, the local frequency being faster than the synchronising frequency, and an interpolator for determining a frequency ratio between the local frequency and the synchronising frequency and for determining an increment value for the counter dependent on a relative amount of a maximum value of the counter with respect to the frequency ratio is disclosed. The counter generates a count value including a predetermined number of bits representing integer values and output as the lower order bits of the output count value and additional lower order bits that represent fractional portions of the integer values. The counter includes output circuitry for outputting the synchronising count value and the predetermined number of bits representing integer values generated by the counter as the lower order bits of the count value.
摘要翻译： 计数值生成器包括用于接收同步计数值的输入，配置为以本地频率递增的计数器，本地频率比同步频率快;以及内插器，用于确定本地频率和同步频率之间的频率比 并且用于根据相对于频率比的计数器的最大值的相对量来确定计数器的增量值。 计数器产生包括表示整数值的预定位数的计数值，并输出为输出计数值的低位位和表示整数值的小数部分的附加低位位。 计数器包括用于输出同步计数值的输出电路和表示由计数器产生的整数值的预定位数作为计数值的低位位。
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公开(公告)号：US20110191543A1
公开(公告)日：2011-08-04
申请号：US12656538
申请日：2010-02-02
CPC分类号： G06F12/0831 , G06F12/0804 , G06F2212/1024 , Y02D10/13
摘要： An apparatus for storing data that is being processed is disclosed. The apparatus comprises: a cache associated with a processor and for storing a local copy of data items stored in a memory for use by the processor, monitoring circuitry associated with the cache for monitoring write transaction requests to the memory initiated by a further device, the further device being configured not to store data in the cache. The monitoring circuitry is responsive to detecting a write transaction request to write a data item, a local copy of which is stored in the cache, to block a write acknowledge signal transmitted from the memory to the further device indicating the write has completed and to invalidate the stored local copy in the cache and on completion of the invalidation to send the write acknowledge signal to the further device.
摘要翻译： 公开了一种用于存储正在处理的数据的装置。 该装置包括：与处理器相关联的用于存储在存储器中用于由处理器使用的数据项的本地副本的高速缓存，用于监控与高速缓存相关联的监视电路，用于监视由另一设备发起的存储器的写事务请求， 进一步的设备被配置为不将数据存储在高速缓存中。 监视电路响应于检测到写入事务请求来写入其本地副本存储在高速缓存中的数据项，以阻止从存储器发送到指示写入已完成的另一设备的写入确认信号，并使其无效 存储的本地副本在缓存中并完成无效，以将写入确认信号发送到另一个设备。
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公开(公告)号：US20110179255A1
公开(公告)日：2011-07-21
申请号：US12656246
申请日：2010-01-21
CPC分类号： G06F11/0793 , G06F1/24
摘要： A processor 4 is provided with reset circuitry 48 which generates a reset signal to reset a plurality of state parameters. Partial reset circuitry 50 is additionally provided to reset a proper subset of this plurality of state parameters. The reset circuitry triggers a redirection of program flow. The partial reset circuitry permits a continuation of program flow. The partial reset circuitry may be used to place processors into a known state with a low latency before switching from a split mode of operation into a locked mode of operation.
摘要翻译： 处理器4设置有复位电路48，其产生复位信号以复位多个状态参数。 另外提供部分复位电路50以复位该多个状态参数的正确子集。 复位电路触发程序流的重定向。 部分复位电路允许继续程序流程。 部分复位电路可以用于在从分离操作模式切换到锁定操作模式之前将处理器置于具有低延迟的已知状态。
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