公开(公告)号：US20070050553A1

公开(公告)日：2007-03-01

申请号：US11307073

申请日：2006-01-23

Applicant: Ting-Cheng Hsu ,  Yen-Yu Lin ,  Chih-Wei Ko ,  Chang-Fu Lin

Inventor： Ting-Cheng Hsu ,  Yen-Yu Lin ,  Chih-Wei Ko ,  Chang-Fu Lin

IPC: G06F12/00

CPC classification number: G06F12/0848 ,  G06F12/0857 ,  G06F12/0897

Abstract: A processing module with multilevel cache architecture, including: a processor; a level-one (L1) cache, coupled to the processor, for caching data for the processor, wherein the L1 cache has at least one L1 cacheable range; a level-two (L2) cache, coupled to the L1 cache, for caching data for the processor, wherein the L2 cache has at least one L2 cacheable range, and the L1 cacheable range and the L2 cacheable range are mutually exclusive; and a memory interface, coupled to the L1 cache and the L2 cache, for transferring data between the L1 cache and a memory and for transferring data between the L2 cache and the memory.

Abstract translation: 具有多级缓存架构的处理模块，包括：处理器; 耦合到所述处理器的用于高速缓存用于所述处理器的数据的一级缓存（L 1），其中所述L 1高速缓存具有至少一个L 1可缓存范围; 耦合到所述L1缓存的二级（L2）高速缓存，用于缓存用于所述处理器的数据，其中所述L 2高速缓存具有至少一个L 2可缓存范围，并且所述L 1可缓存范围和所述L 2可缓存范围 是相互排斥的 以及耦合到L 1缓存和L 2高速缓存的存储器接口，用于在L 1高速缓存和存储器之间传送数据，并用于在L 2高速缓存和存储器之间传送数据。

公开(公告)号：US20060200630A1

公开(公告)日：2006-09-07

申请号：US11419202

申请日：2006-05-19

Applicant: Chang-Fu Lin

Inventor： Chang-Fu Lin

IPC: G06F12/00

CPC classification number: G06F9/3802 ,  G06F9/3808

Abstract: In a method for fetching instructions in an embedded system, a predicted one of a set of the instructions stored in a memory device is fetched and is subsequently stored in an instruction buffer when a system bus is in a data access phase. When a processor generates an access request for the memory device, the predicted one of the instructions stored in the instruction buffer is provided to the system bus for receipt by the processor upon determining that the predicted one of the instructions stored in the instruction buffer hits the access request from the processor. An embedded system with an instruction prefetching device is also disclosed.

Abstract translation: 在用于在嵌入式系统中取指令的方法中，当系统总线处于数据访问阶段时，存储在存储器件中的一组指令中的预测的一个指令被取出并随后被存储在指令缓冲器中。 当处理器产生对存储器件的访问请求时，存储在指令缓冲器中的指令中的预测的一个指令被提供给系统总线，以便在确定存储在指令缓冲器中的预测指令之一被命中时被处理器接收 来自处理器的访问请求。 还公开了一种具有指令预取装置的嵌入式系统。

公开(公告)号：US20060017145A1

公开(公告)日：2006-01-26

申请号：US11212182

申请日：2005-08-26

Applicant: Chang-Fu Lin ,  Han-Ping Pu ,  Cheng-Hsu Hsiao ,  Chien Huang

Inventor： Chang-Fu Lin ,  Han-Ping Pu ,  Cheng-Hsu Hsiao ,  Chien Huang

IPC: H01L23/06

CPC classification number: H01L23/36 ,  H01L23/3675 ,  H01L23/49816 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16315 ,  H01L2924/19105 ,  H01L2924/00014

Abstract: A semiconductor package with a heat sink is provided in which at least one chip is mounted on the substrate and covered by a heat sink. The heat sink is formed with a plurality of grooves or holes at positions in contact with the substrate, allowing an adhesive material to be applied between the heat sink and the substrate and filled into the grooves or holes for attaching the heat sink onto the substrate. The adhesive material filled into the grooves or holes provides an anchoring effect for firmly positioning the heat sink on the substrate. Therefore, it is not necessary to form predetermined holes on the substrate for being coupled to fixing members such as bolts, and incorporation of the heat sink would not affect trace routability and arrangement of input/output connections such as solder balls on the substrate and would not lead to cracks of the chip.

Abstract translation: 提供了具有散热器的半导体封装，其中至少一个芯片安装在基板上并被散热器覆盖。 散热器在与基板接触的位置处形成有多个凹槽或孔，允许将粘合材料施加在散热器和基板之间并填充到用于将散热器附接到基板上的凹槽或孔中。 填充到槽或孔中的粘合剂材料提供了将散热器牢固地定位在基板上的锚固效果。 因此，不需要在基板上形成预定的孔，用于连接诸如螺栓的固定构件，并且散热器的结合不会影响迹线布线性以及诸如衬底上的焊球等输入/输出连接的布置 不会导致芯片的裂纹。

公开(公告)号：US20050040524A1

公开(公告)日：2005-02-24

申请号：US10909029

申请日：2004-07-30

Applicant: Han-Ping Pu ,  Chang-Fu Lin ,  Chien-Ping Huang

Inventor： Han-Ping Pu ,  Chang-Fu Lin ,  Chien-Ping Huang

IPC: H01L23/498 ,  H01L23/48

CPC classification number: H01L23/49816 ,  H01L23/49838 ,  H01L2224/16 ,  H01L2924/01079 ,  H01L2924/15311

Abstract: A chip carrier for a semiconductor chip is provided. A plurality of solder pads for bump soldering are formed on a chip mounting surface of the chip carrier, to allow a flip chip to be mounted and electrically connected to the chip carrier. A solder mask layer is formed on the chip carrier, wherein a plurality of openings are provided in the solder mask layer to expose the solder pads, and an outwardly opening extended portion is formed respectively from the openings corresponding to the solder pads having a relatively narrower pitch therebetween, so as to prevent formation of voids during an underfill process for filing a gap between the flip chip and the chip carrier.

Abstract translation: 提供了一种用于半导体芯片的芯片载体。 在芯片载体的芯片安装表面上形成用于凸块焊接的多个焊盘，以允许倒装芯片安装并电连接到芯片载体。 在芯片载体上形成焊料掩模层，其中在焊料掩模层中设置多个开口以露出焊盘，并且从对应于具有相对较窄的焊盘的开口分别形成向外开口的延伸部分 间隔，以防止在底部填充过程中形成空隙，以便在倒装芯片和芯片载体之间填充间隙。

公开(公告)号：US06578097B1

公开(公告)日：2003-06-10

申请号：US09651423

申请日：2000-08-30

Applicant: Chang-Fu Lin ,  Chih-Jou Lin

Inventor： Chang-Fu Lin ,  Chih-Jou Lin

IPC: G06F100

CPC classification number: G06F13/423 ,  G06F13/4068

Abstract: A method and apparatus for transmitting registered data onto a PCI bus is provided, which can reduce the delay time of manipulating the outgoing signals without greatly increasing the circuit complexity. The apparatus employee a 2R1W data buffer to send a current phase data and a next phase data one clock cycle ahead of the actual AD activity on PCI bus and use a multiplexer to select the current phase data or the next phase data according to a select signal. The select signal is outputted by a OR gate with IRDY# and TRDY# signals as its inputs. Then, the apparatus use a flip-flop to toggling the output signal of the multiplexer to the PCI bus at the actual AD activity. Therefore, the apparatus of the present invention not only reduce the delay time of manipulating the outgoing signals, but also is implemented with simple architecture.

Abstract translation: 提供一种将注册数据发送到PCI总线上的方法和装置，其可以减少操纵输出信号的延迟时间，而不会大大增加电路复杂度。 该设备雇员一个2R1W数据缓冲器，用于在PCI总线上的实际AD活动之前一个时钟周期发送当前相位数据和下一个相位数据，并使用多路复用器根据选择信号选择当前相位数据或下一个相位数据 。 选择信号由IRDY＃和TRDY＃信号作为其输入的或门输出。 然后，该设备使用触发器在实际的AD活动下切换多路复用器的输出信号到PCI总线。 因此，本发明的装置不仅减少了操纵输出信号的延迟时间，而且还以简单的架构来实现。