公开(公告)号：US5751624A

公开(公告)日：1998-05-12

申请号：US715732

申请日：1996-09-19

Applicant: Changming Zhou ,  Guoliang Shou ,  Makoto Yamamoto ,  Sunao Takatori

Inventor： Changming Zhou ,  Guoliang Shou ,  Makoto Yamamoto ,  Sunao Takatori

IPC: G06G7/22 ,  G06J1/00 ,  G06C15/08

CPC classification number: G06G7/22 ,  G06J1/00

Abstract: A complex number calculation circuit for directly multiplying a complex number of an analog signal by a digital complex number as a multiplier. A capacitive coupling is used with a plurality of parallel capacitances corresponding to weights of bits of real and imaginary parts of the multiplier. The sign of the multiplier is represented by selection of output paths. A complex number calculation circuit for calculating approximated absolute values is suitable for an analog architecture. Inverter circuits are used for linear inversion of analog values, and capacitive couplings are used for weighted addition. Analog maximum and minimum circuits with parallel MOSs are used for maximum and minimum calculation.

Abstract translation: 一种用于将复数个模拟信号乘以数字复数作为乘数的复数计算电路。 电容耦合用于与乘法器的实部和虚部的位的权重相对应的多个并联电容。 乘法器的符号由输出路径的选择表示。 用于计算近似绝对值的复数计算电路适用于模拟架构。 逆变电路用于模拟值的线性反演，电容耦合用于加权相加。 具有并联MOS的模拟最大和最小电路用于最大和最小计算。

公开(公告)号：US6081549A

公开(公告)日：2000-06-27

申请号：US4607

申请日：1998-01-08

Applicant: Guoliang Shou ,  Changming Zhou ,  Xuping Zhou

Inventor： Guoliang Shou ,  Changming Zhou ,  Xuping Zhou

IPC: H04B1/707 ,  H04B1/712 ,  H04B7/01 ,  H04B7/08 ,  H04K1/00

CPC classification number: H04B1/711 ,  H04B7/01 ,  H04B1/7093 ,  H04B1/7117 ,  H04B2201/70701

Abstract: Phases of the spread spectrum signal are corrected with a high degree of accuracy by a minimum of circuitry. One of phase correction circuits 31-34 of the receiver corresponds to each path. The I-component and Q-component of a despread output are supplied to the phase correction circuits 31-34. A phase error extractor 1 extracts the first phase error from a received pilot block. A phase corrector 2 corrects the phase error of a received information symbol using a correction vector that has been calculated based on the first phase error. The RAKE synthesizer 25 synthesizes the corrected received signal with outputs of the phase correction A circuits of other paths and outputs the synthesized signal to a temporary determiner 3 which temporarily determines an information symbol to be processed. The phase error is modified in a correction vector modifier 4 using the temporary determination result. A new correction vector is calculated based on the modified phase error. In this way, the correction vectors are sequentially modified based on the temporary determination results for the information symbols.

Abstract translation: 通过最小的电路以高精度校正扩频信号的相位。 接收机的相位校正电路31-34中的一个对应于每个路径。 解扩输出的I分量和Q分量被提供给相位校正电路31-34。 相位误差提取器1从接收到的导频块中提取第一相位误差。 相位校正器2使用已经基于第一相位误差计算的校正矢量校正接收信息符号的相位误差。 RAKE合成器25将校正的接收信号与其他路径的相位校正A电路的输出合成，并将合成信号输出到暂时确定要处理的信息符号的临时确定器3。 使用临时确定结果在校正矢量修改器4中修改相位误差。 基于修正的相位误差计算新的校正矢量。 以这种方式，基于信息符号的临时确定结果，顺序修改校正矢量。

公开(公告)号：US06064690A

公开(公告)日：2000-05-16

申请号：US75861

申请日：1998-05-12

Applicant: Changming Zhou ,  Xuping Zhou ,  Guolinag Shou

Inventor： Changming Zhou ,  Xuping Zhou ,  Guolinag Shou

IPC: H04B1/707 ,  H04B1/69

CPC classification number: H04B1/707 ,  H04B1/7093

Abstract: A spread spectrum communication system wherein spreading codes for in-phase and quadrature components are composed by addition and subtraction and the received signal is multiplied by these composed codes for despreading. The communication system comprises a transmitter generating in-phase and quadrature components. The transmitter includes a spreading circuit for spreading the in-phase and quadrature components. The system further includes a receiver, a phase correction circuit for correcting the phase of despreaded components, a rake combiner for combining the components corrected by the phase correction circuit and a circuit for outputting a combined signal and a delay detection circuit for delaying detection of the combined signal. The receiver also comprises a provisional judgment portion for judging the phase of a pair of the in-phase and quadrature phase components. The phase correction circuit corrects the phase according to the phase judged by the provisional judgment portion.

Abstract translation: 扩展频谱通信系统，其中用于同相和正交分量的扩展码由加法和减法组成，并且接收的信号乘以这些组合代码用于解扩。 通信系统包括产生同相和正交分量的发射机。 发射机包括用于扩展同相和正交分量的扩展电路。 该系统还包括接收机，用于校正解扩部件的相位的相位校正电路，用于组合由相位校正电路校正的分量的组合器和用于输出组合信号的电路和延迟检测电路的延迟检测电路 组合信号。 接收机还包括用于判断一对同相和正交相位分量的相位的临时判断部分。 相位校正电路根据由临时判断部判定的相位来校正相位。

公开(公告)号：US5958002A

公开(公告)日：1999-09-28

申请号：US905784

申请日：1997-08-12

Applicant: Changming Zhou ,  Guoliang Shou ,  Kunihiko Suzuki ,  Kazunori Motohashi ,  Makoto Yamamoto ,  Sunao Takatori

Inventor： Changming Zhou ,  Guoliang Shou ,  Kunihiko Suzuki ,  Kazunori Motohashi ,  Makoto Yamamoto ,  Sunao Takatori

IPC: G06G7/25 ,  G06G7/22 ,  G06G7/00 ,  G06G7/16

CPC classification number: G06G7/22

Abstract: A highly accurate vector absolute-value calculation circuit uses analog processing and minimal hardware. Signal voltages corresponding to an I component (real number part) and a Q component (imaginary number part) are input to a first absolute-value calculation circuit 13 and a second absolute-value calculation circuit 14 through terminals 11 and 12, respectively, and they are each converted into absolute-value signals. The component I absolute-value and component Q absolute-value are compared in a comparison circuit 20. According to the result, the larger absolute-value signals are output to an input capacitor 23 of a neural computation circuit, and the smaller absolute-value signals are output to an input capacitor 24 by controlling multiplexers 21 and 22. The capacity ratio of a feedback capacitor 26 of a neural computation circuit and input capacitors 23 and 24 is 11:10:5. The complex number absolute-value calculated by the following formula is output from an output terminal 27. ##EQU1##

Abstract translation: 高精度矢量绝对值计算电路采用模拟处理和最小硬件。 对应于I分量（实数部分）和Q分量（虚数部分）的信号电压分别通过端子11和12输入到第一绝对值计算电路13和第二绝对值计算电路14，以及 它们都被转换为绝对值信号。 在比较电路20中比较分量I绝对值和分量Q绝对值。根据结果，较大的绝对值信号被输出到神经计算电路的输入电容器23，并且较小的绝对值 通过控制多路复用器21和22将信号输出到输入电容器24.神经计算电路和输入电容器23和24的反馈电容器26的容量比为11:10:5。 从输出端子27输出由下式计算的复数绝对值。

公开(公告)号：US5956333A

公开(公告)日：1999-09-21

申请号：US781631

申请日：1997-01-10

Applicant: Changming Zhou ,  Guoliang Shou ,  Kenzo Urabe ,  Tetsuhiko Miyatani

Inventor： Changming Zhou ,  Guoliang Shou ,  Kenzo Urabe ,  Tetsuhiko Miyatani

IPC: H03H17/00 ,  H04B1/7107 ,  H04J13/00 ,  H04K1/00

CPC classification number: H04B1/71075

Abstract: A multi-user demodulator eliminates synchronization problems without interference cancellation. A threshold process is applied to a despread signal to extract each user's signal. The extracted signals are respread, and those respread signals other than a specifier user's signal are subtracted from the received signal to ideally extract the specific user's signal.

Abstract translation: 多用户解调器消除了无干扰消除的同步问题。 对解扩信号应用阈值处理以提取每个用户的信号。 提取的信号被重新发送，并且从接收到的信号中减去除指定者用户信号之外的那些再现信号，以理想地提取特定用户的信号。

公开(公告)号：US5930157A

公开(公告)日：1999-07-27

申请号：US895272

申请日：1997-07-16

Applicant: Ichiro Matsumoto ,  Changming Zhou ,  Guoliang Shou

Inventor： Ichiro Matsumoto ,  Changming Zhou ,  Guoliang Shou

IPC: G06F17/10 ,  G06F17/15 ,  G06J1/00 ,  G06F7/12

CPC classification number: G06J1/00

Abstract: The autocorrelation coefficient operator 60 carries out an integration operation to determine the autocorrelation coefficient for audio signal processing or other types of signal processing at high speed with low power consumption. The input signal S is digitized in the A/D converter 30 to the digital signal SP and supplied to a delay unit 40, which delays and holds the digital signal SP sequentially. A sample holder 45 also samples and holds the analog signal S in synchronization with the delay unit 40. When the number of sampled values held by the sample holder 45 reaches a predetermined value, the sample holder 45 outputs the sampled values at the same time in accordance with a sampling clock signal CK which is supplied by a clock signal generator 35. Delayed values held in the delay unit 40 are shifted and output sequentially in accordance with a shift clock signal SCK, the frequency of which is higher than that of the sampling clock signal CK. A weighted addition circuit 50 integrates these sampled values and the delayed values to calculate the autocorrelation coefficient R.

Abstract translation: 自相关系数运算器60执行积分运算，以低功耗确定音频信号处理的自相关系数或其他类型的信号处理。 输入信号S在A / D转换器30中数字化为数字信号SP，并提供给延迟单元40，延迟单元40依次延迟和保持数字信号SP。 样本保持器45还与延迟单元40同步地采样并保持模拟信号S.当采样保持器45保持的采样值的数量达到预定值时，样本保持器45同时输出采样值 根据由时钟信号发生器35提供的采样时钟信号CK。保持在延迟单元40中的延迟值根据频率高于采样的移位时钟信号SCK被顺序移位和输出 时钟信号CK。 加权加法电路50对这些采样值和延迟值进行积分，以计算自相关系数R.

公开(公告)号：US5815812A

公开(公告)日：1998-09-29

申请号：US760257

申请日：1996-12-05

Applicant: Changming Zhou ,  Guoliang Shou ,  Makoto Yamamoto ,  Mamoru Sawahashi ,  Fumiyuki Adachi ,  Sunao Takatori

Inventor： Changming Zhou ,  Guoliang Shou ,  Makoto Yamamoto ,  Mamoru Sawahashi ,  Fumiyuki Adachi ,  Sunao Takatori

IPC: H04J13/00 ,  H04B1/7093 ,  H04W36/18 ,  H04W36/36 ,  H04Q7/32

CPC classification number: H04B1/7093 ,  H04W36/18

Abstract: The present invention provides a system for soft handoff, which processes in high speed. A system according to the present invention substantially realizes a multiplication by a circuit for classifying received signals from a plurality of cell site stations once held in an analog sampling and holding circuit into two groups, multiplication and accumulation, by a small circuit of low electric power consumption.

Abstract translation: 本发明提供了一种用于软切换的系统，其高速处理。 根据本发明的系统基本上实现了一种电路的乘法，该电路用于将一次保持在模拟采样和保持电路中的多个小区站点的接收信号分类成两组，通过低功率的小电路进行乘法和累加 消费。

公开(公告)号：US5815021A

公开(公告)日：1998-09-29

申请号：US686761

申请日：1996-07-26

Applicant: Guoliang Shou ,  Changming Zhou ,  Kazunori Motohashi ,  Makoto Yamamoto ,  Sunao Takatori

Inventor： Guoliang Shou ,  Changming Zhou ,  Kazunori Motohashi ,  Makoto Yamamoto ,  Sunao Takatori

IPC: G06G7/14 ,  G06J1/00 ,  G06G7/16

CPC classification number: G06J1/00 ,  G06G7/14

Abstract: The present invention provides a weighted addition circuit for sampling, holding and performing weighted addition by a circuit smaller than a conventional one. In the weighted addition circuit of to the present invention, a capacitive coupling is connected to a plurality of switches which are further connected only to an input voltage. A voltage is held and a weight is added in the capacitive coupling.

Abstract translation: 本发明提供一种加权加法电路，用于通过比传统电路小的电路进行采样，保持和执行加权相加。 在本发明的加权加法电路中，电容耦合连接到多个开关，该开关进一步仅与输入电压相连。 在电容耦合中保持电压并加上重量。

公开(公告)号：US06563373B1

公开(公告)日：2003-05-13

申请号：US09165301

申请日：1998-10-02

Applicant: Guoliang Shou ,  Kunihiko Suzuki ,  Changming Zhou

Inventor： Guoliang Shou ,  Kunihiko Suzuki ,  Changming Zhou

IPC: H03H1502

CPC classification number: H04B1/7093 ,  H03H11/04

Abstract: An analog calculation circuit in a filter circuit is corrected in the calculation error by estimating the error from a calculation result of known inputs and known multiplier. A multiplier is changed according to the estimated error. The filter circuit has a voltage to current converter at an input side and a current to voltage converter at an output side and a calculation of current is performed therein.

Abstract translation: 滤波器电路中的模拟计算电路通过从已知输入和已知乘数的计算结果估计误差来校正计算误差。 根据估计的误差改变乘数。 滤波电路在输入侧具有电压 - 电流转换器，在输出侧具有电流 - 电压转换器，并且在其中执行电流计算。

公开(公告)号：US06539009B1

公开(公告)日：2003-03-25

申请号：US09195162

申请日：1998-11-18

Applicant: Changming Zhou ,  Xuping Zhou ,  Mamoru Sawahashi ,  Fumiyuki Adachi

Inventor： Changming Zhou ,  Xuping Zhou ,  Mamoru Sawahashi ,  Fumiyuki Adachi

IPC: H04B1707

CPC classification number: H04B1/707

Abstract: A plurality of sets of spreading code sequences are stored in registers and selectively supplied to matched filters. The soft-handover, multi-code processing and long-delay paths can be processed by a small circuit.

Abstract translation: 多组扩展码序列被存储在寄存器中并选择性地提供给匹配的滤波器。 软切换，多码处理和长延迟路径可以由小电路处理。