公开(公告)号：US20110139611A1

公开(公告)日：2011-06-16

申请号：US12963193

申请日：2010-12-08

Applicant: Beong-Ju Kim ,  Ji-Su Ahn ,  Cheol-Ho Yu ,  Sung-Chul Kim

Inventor： Beong-Ju Kim ,  Ji-Su Ahn ,  Cheol-Ho Yu ,  Sung-Chul Kim

IPC: C23C16/24 ,  C23C14/34 ,  C23C14/14

CPC classification number: H01L21/67184 ,  H01L21/67196 ,  H01L21/67201

Abstract: In an apparatus for fabricating a thin film transistor, amorphous silicon is deposited on a substrate in a first multi-chamber and is crystallized into polycrystalline silicon without using a separate process chamber or multi-chamber, and the substrate deposited with the amorphous silicon is loaded into a second multi-chamber for forming electrodes, thereby making it possible to minimize a characteristic deviation and improve fabrication process efficiency. The apparatus includes a first multi-chamber in which amorphous silicon is deposited on a substrate, a second multi-chamber in which electrodes are formed on the substrate, and a loading/unloading chamber interposed between the first multi-chamber and the second multi-chamber. The loading/unloading chamber includes a substrate holder on a lower side thereof and a power voltage supplier on an upper side thereof.

Abstract translation: 在用于制造薄膜晶体管的装置中，非晶硅沉积在第一多腔中的衬底上，并且在不使用单独的处理室或多腔的情况下被结晶成多晶硅，并且将沉积有非晶硅的衬底加载 进入用于形成电极的第二多室中，从而使得可以使特性偏差最小化并提高制造工艺效率。 该装置包括：第一多腔室，其中非晶硅沉积在基底上;第二多腔室，其中在基底上形成电极;以及装载/卸载室，介于第一多腔室和第二多腔室之间， 房间。 装载/卸载室包括在其下侧的基板保持件和在其上侧的电源电压供应器。

公开(公告)号：US20090278131A1

公开(公告)日：2009-11-12

申请号：US12385792

申请日：2009-04-20

Applicant: Do-Hyun Kwon ,  Choong-Youl Im ,  Dae-Hyun No ,  Il-Jeong Lee ,  Cheol-Ho Yu

Inventor： Do-Hyun Kwon ,  Choong-Youl Im ,  Dae-Hyun No ,  Il-Jeong Lee ,  Cheol-Ho Yu

IPC: H01L33/00 ,  H01L21/28

CPC classification number: H01L27/1255 ,  H01L27/1288 ,  H01L2227/323

Abstract: A thin film transistor (TFT) array arrangement, an organic light emitting display device that includes the TFT array arrangement and a method of making the TFT array arrangement and the organic light emitting display device. The method seeks to reduce the number of masks used in the making of the TFT array arrangement by employing half-tone masks that are followed by a two step etching process and by forming layers of the capacitor simultaneous with the formation of layers of the source, drain and pixel electrodes. As a result, individual layers of the capacitor are on the same level and are made of the same material as ones of the layers of the source, drain and pixel electrodes. The capacitor has three electrodes spaced apart by two separate dielectric layers to result in an increased capacity capacitor without increasing the size of the capacitor.

Abstract translation: 薄膜晶体管（TFT）阵列布置，包括TFT阵列布置的有机发光显示装置和制造TFT阵列布置的方法和有机发光显示装置。 该方法通过采用半色调掩模来减少用于制造TFT阵列布置的掩模的数量，其后面是两步蚀刻工艺，并且通过在形成层的同时形成电容层， 漏极和像素电极。 结果，电容器的各个层位于同一水平上，并且由与源极，漏极和像素电极的层相同的材料制成。 电容器具有通过两个单独的电介质层隔开的三个电极，从而在不增加电容器尺寸的情况下产生增加的容量电容器。