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公开(公告)号：US08736628B1
公开(公告)日：2014-05-27
申请号：US10846192
申请日：2004-05-14
CPC分类号： G06T1/60 , G06T1/20 , G06T15/005
摘要： A present invention pixel processing system and method permit complicated three dimensional images to be rendered with shallow graphics pipelines including reduced gate counts and facilitates power conservation by utilizing a single unified data fetch stage (e.g., unified data fetch module) that retrieves a variety of different pixel surface attribute values for different attribute types (e.g., depth, color, and/or texture values) in a single stage. Different types of pixel surface attribute data (e.g., depth, color, texture) associated with multiple graphics processing functions (e.g., color blending, texture mapping, etc.) are retrieved in the single unified data fetch graphics pipeline stage. The pixel packet rows including the pixel surface attribute values are forwarded to other graphics pipeline stages for single thread processing (e.g. to a universal arithmetic logic unit capable of performing multiple graphics functions on the pixel surface attribute values).
摘要翻译： 本发明的像素处理系统和方法允许使用包括减少的门数的浅图形管线来呈现复杂的三维图像，并且通过利用单个统一的数据提取阶段（例如，统一的数据获取模块）来简化功率节省，该统一数据获取阶段检索各种不同的 单个阶段中不同属性类型（例如，深度，颜色和/或纹理值）的像素表面属性值。 在单个统一数据提取图形流水线阶段检索与多个图形处理功能（例如，颜色混合，纹理映射等）相关联的不同类型的像素表面属性数据（例如，深度，颜色，纹理）。 包括像素表面属性值的像素分组行被转发到用于单线程处理的其他图形流水线级（例如，到能够对像素表面属性值执行多个图形功能的通用算术逻辑单元）。
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公开(公告)号：US08599208B2
公开(公告)日：2013-12-03
申请号：US11893622
申请日：2007-08-15
申请人： Tyson J. Bergland , Craig M. Okruhlica , Edward A. Hutchins , Michael J. M. Toksvig , Justin M. Mahan
发明人： Tyson J. Bergland , Craig M. Okruhlica , Edward A. Hutchins , Michael J. M. Toksvig , Justin M. Mahan
CPC分类号： G09G5/363 , G06F9/30098 , G06F9/3879 , G06T1/20 , G06T15/005
摘要： An arithmetic logic stage in a graphics processor unit includes arithmetic logic units (ALUs) and global registers. The registers contain global values for a group of pixels. Global values may be read from any of the registers, regardless of which of the pixels is being operated on by the ALUs. However, when writing results of the ALU operations, only some of the global registers are candidates to be written to, depending on the pixel number. Accordingly, overwriting of data is prevented.
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33.发明授权公开(公告)号：US08547395B1
公开(公告)日：2013-10-01
申请号：US11643545
申请日：2006-12-20
IPC分类号： G09G5/00
CPC分类号： G06T15/005 , G06T11/40
摘要： A computer-implemented graphics system has a mode of operation in which primitive coverage information is generated by a rasterizer for real sample locations and virtual sample locations for use in anti-aliasing. An individual pixel includes a single real sample location and at least one virtual sample location. If the coverage information cannot be changed by a pixel shader, then the rasterizer can write the coverage information to a framebuffer. If, however, the coverage information can be changed by the shader, then the rasterizer sends the coverage information to the shader.
摘要翻译： 计算机实现的图形系统具有操作模式，其中原始覆盖信息由光栅化器生成用于实际样本位置和用于抗锯齿的虚拟样本位置。 单个像素包括单个实际采样位置和至少一个虚拟采样位置。 如果覆盖信息不能被像素着色器改变，则光栅化器可以将覆盖信息写入帧缓冲区。 然而，如果覆盖信息可以由着色器改变，则光栅化器将覆盖信息发送到着色器。
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公开(公告)号：US07969446B2
公开(公告)日：2011-06-28
申请号：US11374947
申请日：2006-03-13
申请人： Edward A. Hutchins , Brian K. Angell , Paul Kim
发明人： Edward A. Hutchins , Brian K. Angell , Paul Kim
IPC分类号： G09G5/37
CPC分类号： G06T15/005 , G06F9/3001 , G06F9/30025 , G06T1/20
摘要： A graphics processor is disclosed having a programmable Arithmetic Logic Unit (ALU) stage for processing pixel packets. Scalar arithmetic operations are performed in the ALUs to implement a graphics function.
摘要翻译： 公开了具有用于处理像素分组的可编程算术逻辑单元（ALU）级的图形处理器。 在ALU中执行标量算术运算以实现图形功能。
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35.发明授权System and method for pixel data row forwarding in a 3-D graphics pipeline 有权3-D图形流水线中像素数据行转发的系统和方法公开(公告)号：US07868902B1
公开(公告)日：2011-01-11
申请号：US10846773
申请日：2004-05-14
申请人： Edward A. Hutchins , Paul Kim
发明人： Edward A. Hutchins , Paul Kim
CPC分类号： G06T15/005
摘要： A system and method for a row forwarding of pixel data in a 3-D graphics pipeline. Specifically, in one embodiment a data write unit capable of row forwarding in a graphics pipeline includes a first memory and logic. The first memory stores a plurality of rows of pixel information associated with a pixel. The plurality of rows of pixel information includes data related to surface characteristics of the pixel and includes a first row, e.g., a front row, and a second row, e.g., a rear row. A data write unit includes first logic for accessing a portion of the second row and for storing data accessed therein into a portion of the first row. The data write unit also comprises logic for recirculating the plurality of rows of pixel information to an upstream pipeline module for further processing thereof.
摘要翻译： 用于在3D图形流水线中行像素数据的行转发的系统和方法。 具体地，在一个实施例中，能够在图形流水线中进行行转发的数据写入单元包括第一存储器和逻辑。 第一存储器存储与像素相关联的多行像素信息。 多行像素信息包括与像素的表面特性有关的数据，并且包括第一行，例如前排，以及第二行，例如后排。 数据写入单元包括用于访问第二行的一部分并将其中访问的数据存储到第一行的一部分中的第一逻辑。 数据写入单元还包括用于将多行像素信息再循环到上游流水线模块以用于进一步处理的逻辑。
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36.发明授权Selecting real sample locations for ownership of virtual sample locations in a computer graphics system 有权选择计算机图形系统中虚拟样本位置的所有权的实际样本位置公开(公告)号：US07817165B1
公开(公告)日：2010-10-19
申请号：US11643185
申请日：2006-12-20
IPC分类号： G09G5/00
CPC分类号： G09G5/363 , G06T11/40 , G09G5/00 , G09G2340/10 , G09G2360/18
摘要： A computer-implemented graphics system has a mode of operation in which primitive coverage information is generated for real sample locations and virtual sample locations for use in anti-aliasing. An individual pixel includes a single real sample location and at least one virtual sample location. A block of real sample locations can be selected to delineate and encompass a region containing a number of virtual sample locations. Pixel attribute values (e.g., z-depth or stencil values) associated with the block of selected real sample locations can be used to associate each virtual sample location within the region with one of the selected real sample locations. The virtual sample location assumes the pixel attribute value of the real sample location with which it is associated.
摘要翻译： 计算机实现的图形系统具有操作模式，其中为实际采样位置和用于抗锯齿的虚拟采样位置生成原始覆盖信息。 单个像素包括单个实际采样位置和至少一个虚拟采样位置。 可以选择实际样本位置的块来描绘并包含包含多个虚拟样本位置的区域。 可以使用与所选择的实取样位置的块相关联的像素属性值（例如，z深度或模板值）将该区域内的每个虚拟样本位置与所选择的实际采样位置之一相关联。 虚拟样本位置假定与其相关联的实际样本位置的像素属性值。
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37.发明授权Arithmetic logic unit and method for processing data in a graphics pipeline 有权用于在图形管线中处理数据的算术逻辑单元和方法公开(公告)号：US07710427B1
公开(公告)日：2010-05-04
申请号：US10846728
申请日：2004-05-14
CPC分类号： G09G5/363 , G06F9/3001 , G06F9/30025 , G06F9/30101 , G06F9/30167 , G06T15/005 , G09G5/001 , G09G5/003 , G09G2320/0252 , G09G2360/121 , G09G2370/10
摘要： Embodiments of the present invention include an arithmetic logic unit for use in a graphics pipeline. The arithmetic logic unit comprising a plurality of scalar arithmetic logic subunits wherein each subunit performs a resultant arithmetic logic operation in the form of [a*b “op” c*d] on a set of input operands a, b, c and d. The arithmetic logic unit also for produces a result based thereon wherein “op” represents a programmable operation and wherein further the resultant arithmetic logic operation is software programmable to implement a plurality of different graphics functions.
摘要翻译： 本发明的实施例包括用于图形管线的算术逻辑单元。 算术逻辑单元包括多个标量运算逻辑子单元，其中每个子单元在一组输入操作数a，b，c和d上以[a * b“op”c * d]的形式执行合成算术逻辑运算。 算术逻辑单元还用于产生基于其的结果，其中“op”表示可编程操作，并且其中所得的算术逻辑操作进一步可软件编程以实现多个不同的图形功能。
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公开(公告)号：US07659909B1
公开(公告)日：2010-02-09
申请号：US11973738
申请日：2007-10-09
申请人： Edward A. Hutchins
发明人： Edward A. Hutchins
CPC分类号： G06T1/20 , G06F9/3001 , G06F9/3867 , G09G3/003 , G09G5/363 , G09G2340/145 , G09G2360/125
摘要： An arithmetic logic unit (ALU) in a graphics processor is described. The ALU includes circuitry for performing an operation using a first set of pixel data. The first set of pixel data is resident in a pipeline register coupled to the circuitry. A temporary register is coupled to the circuitry. The temporary register can receive a result of the operation. The temporary register allows a result generated using one set of pixel data to be used with a subsequent set of pixel data in the same ALU. The result of the operation can thus be used in a second operation with a second set of pixel data that resides in the pipeline register after the first set of pixel data.
摘要翻译： 描述图形处理器中的算术逻辑单元（ALU）。 ALU包括用于使用第一组像素数据执行操作的电路。 第一组像素数据驻留在耦合到电路的流水线寄存器中。 临时寄存器耦合到电路。 临时寄存器可以接收到操作的结果。 临时寄存器允许使用一组像素数据生成的结果与同一ALU中的后续像素数据集一起使用。 因此，可以在第二组像素数据的第二操作中使用该操作的结果，该第二组像素数据位于第一组像素数据之后的流水线寄存器中。
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公开(公告)号：US20090147012A1
公开(公告)日：2009-06-11
申请号：US12001251
申请日：2007-12-10
IPC分类号： G06T1/00
CPC分类号： G06T11/40
摘要： In a graphics pipeline of a graphics processor, a method for a unified primitive description for rasterization. The method includes receiving a group of primitives from a graphics application, wherein the group includes different types of primitives and the types of primitives include line primitives, point primitives and triangle primitives. For each of the types of primitives, the method includes generating a corresponding parallelogram, wherein the parallelogram has four sides disposed along an x-axis and a y-axis, and computing an inside y-axis mid point and an outside y-axis mid point based on the four sides. The parallelogram is controlled to represent to each of the primitive types respectively by adjusting a location of the inside y-axis mid point or the outside y-axis mid point.
摘要翻译： 在图形处理器的图形流水线中，用于光栅化的统一原始描述的方法。 该方法包括从图形应用程序接收一组图元，其中该组包括不同类型的图元，并且图元的类型包括线图元，点基元和三角形图元。 对于每种类型的图元，该方法包括生成对应的平行四边形，其中平行四边形具有沿着x轴和y轴设置的四个边，并且计算内部y轴中点和外部y轴中间 以四方为依据。 控制平行四边形分别通过调整内部y轴中点或外部y轴中点的位置来表示每个基本类型。
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40.发明授权Method and system for implementing parameter clamping to a valid range in a raster stage of a graphics pipeline 有权将参数夹持实现到图形管线的光栅级中的有效范围的方法和系统公开(公告)号：US07538773B1
公开(公告)日：2009-05-26
申请号：US10845987
申请日：2004-05-14
申请人： Edward A. Hutchins
发明人： Edward A. Hutchins
CPC分类号： G06T15/005
摘要： A method of determining pixel parameters, wherein the pixel parameters were clamped to a valid range. The method includes a step of accessing a geometric primitive comprising a plurality of vertices wherein each vertex has associated therewith a plurality of parameters including a pair of texture coordinates. During rasterization of said geometric primitive performed in a rasterization module of graphics pipeline, a respective pair of texture coordinates for each pixel of said geometric primitive are computed using interpolation. Each computed texture coordinate includes an integer portion and a fractional portion. Only the fractional portions of said texture coordinates are propagated to a downstream data fetch module of said graphics pipeline.
摘要翻译： 一种确定像素参数的方法，其中像素参数被钳位到有效范围。 该方法包括访问包括多个顶点的几何图元的步骤，其中每个顶点与其相关联，包括一对纹理坐标的多个参数。 在在图形流水线的光栅化模块中执行的所述几何图元的光栅化期间，使用内插来计算所述几何图元的每个像素的相应对的纹理坐标。 每个计算的纹理坐标包括整数部分和小数部分。 只有所述纹理坐标的小数部分被传播到所述图形管线的下游数据获取模块。
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