公开(公告)号：US5497472A

公开(公告)日：1996-03-05

申请号：US375234

申请日：1995-01-19

申请人： Akira Yamamoto ,  Shigeo Homma ,  Yoshihiro Asaka ,  Yoshiaki Kuwahara ,  Akira Kurano ,  Masafumi Nozawa ,  Hiroyuki Kitajima

发明人： Akira Yamamoto ,  Shigeo Homma ,  Yoshihiro Asaka ,  Yoshiaki Kuwahara ,  Akira Kurano ,  Masafumi Nozawa ,  Hiroyuki Kitajima

IPC分类号： G06F3/06 ,  G06F12/08

CPC分类号： G06F12/0866

摘要： In an information processing system having a data processing apparatus, a control unit for a cache memory, and a storage unit for storing a record, respectively interconnected together, wherein when the control unit receives from the data processing apparatus a write request for a record to be written and if the record to be written is not being stored in the cache memory, the control unit receives a data to be written in the object record from the data processing apparatus and stores the received data in the cache memory. After notifying the data processing apparatus of a completion of a data write process, the control unit checks if the object record in which the data stored in the cache memory is being stored in the storage unit, if the object record is being stored in the storage unit, the data in the cache memory is written in the storage unit, and if not, the data in the cache memory is not written and such effect is notified to the data processing apparatus.

摘要翻译： 在具有数据处理装置，高速缓冲存储器的控制单元和分别互连在一起的记录的存储单元的信息处理系统中，其中当控制单元从数据处理装置接收到对记录的写请求时， 写入，并且如果要写入的记录未被存储在高速缓冲存储器中，则控制单元从数据处理装置接收要写入对象记录中的数据，并将接收到的数据存储在高速缓冲存储器中。 在通知数据处理装置完成数据写入处理之后，如果对象记录被存储在存储单元中，则控制单元检查存储在高速缓冲存储器中的数据是否存储在存储单元中的对象记录 高速缓冲存储器中的数据被写入存储单元中，如果不存在，则高速缓冲存储器中的数据不被写入，并且将该效果通知给数据处理装置。

公开(公告)号：US5193154A

公开(公告)日：1993-03-09

申请号：US783718

申请日：1991-10-25

申请人： Hiroyuki Kitajima ,  Akira Yamamoto ,  Takashi Doi ,  Masafumi Nozawa

发明人： Hiroyuki Kitajima ,  Akira Yamamoto ,  Takashi Doi ,  Masafumi Nozawa

IPC分类号： G06F13/00

CPC分类号： G06F13/00 ,  Y10S707/99955

摘要： A buffered peripheral system comprises a backup memory and a primary control unit which has a buffer memory for temporarily storing a copy of the contents of a buffer memory which stores data to be written to a peripheral device and a control device for issuing a command necessary to write the block stored in the buffer memory device to the peripheral device. The primary control unit also includes a recording device for recording the block number corresponding to the block which was most recently written to the peripheral device. The blocks of data which have been written to the peripheral device is then deleted from the backup memory to make room for storing further blocks of data. The system further has a backup control unit substantially identical to the primary control unit. Only the primary control unit normally operates to control the writing to the peripheral device. Upon detection of the failure of the buffer memory in the primary control unit, the backup control unit completes the operation of writing to the peripheral device by retrieving the blocks of data to be written to the peripheral device from the backup memory device using the block number information.

摘要翻译： 缓冲外设系统包括备用存储器和主控单元，该主控制单元具有缓冲存储器，用于临时存储要写入外围设备的数据的缓冲存储器的内容副本以及用于发出必要的命令的控制装置 将存储在缓冲存储器件中的块写入外围设备。 主控制单元还包括用于记录与最近写入外围设备的块相对应的块号的记录装置。 已经写入外围设备的数据块然后从备份存储器中删除，为存储更多的数据块腾出空间。 该系统还具有与主控制单元基本相同的备用控制单元。 只有主控制单元通常操作才能控制对外围设备的写入。 在检测到主控制单元中的缓冲存储器的故障时，备用控制单元通过使用块号从备用存储装置检索要写入外围设备的数据块来完成对外围装置的写入操作 信息。

公开(公告)号：US4967341A

公开(公告)日：1990-10-30

申请号：US418343

申请日：1989-10-06

申请人： Akira Yamamoto ,  Tadashi Ohsone ,  Masashi Tsuchida ,  Hiroyuki Kitajima ,  Kazuhiro Satoh ,  Yoshiaki Yamashita ,  Nobuhiro Taniguchi ,  Kazuhiko Ohmachi ,  Shinichi Fukushima

发明人： Akira Yamamoto ,  Tadashi Ohsone ,  Masashi Tsuchida ,  Hiroyuki Kitajima ,  Kazuhiro Satoh ,  Yoshiaki Yamashita ,  Nobuhiro Taniguchi ,  Kazuhiko Ohmachi ,  Shinichi Fukushima

IPC分类号： G06F17/30

CPC分类号： G06F17/30501 ,  G06F17/30498 ,  Y10S707/99932

摘要： A set of sorted columns of one table stored in a DB machine are binary-searched by a hardware in synchronism with data transfer when another table is read from a disk unit, to select a row to be joined. Where a key word sequence to be searched is stored in ascending or descending order, determination of a maximum address in an area in which key words smaller than a search key are stored and determination of a maximum address in an area in which the key words smaller than or equal to the search key are stored are parallelly executed to determine the store range in one searching.

摘要翻译： 存储在DB机器中的一个表的一组排序列由硬件与数据传输同步地进行二进制搜索，当从磁盘单元读取另一个表时，选择要连接的行。 在要搜索的关键字序列以升序或降序存储的情况下，确定存储关键字小于搜索关键字的区域中的最大地址，并确定关键字较小的区域中的最大地址 存储的搜索关键字大于或等于并行执行，以便在一次搜索中确定存储范围。

公开(公告)号：US08588256B2

公开(公告)日：2013-11-19

申请号：US12961463

申请日：2010-12-06

申请人： Toru Katagiri ,  Hiroyuki Kitajima

发明人： Toru Katagiri ,  Hiroyuki Kitajima

IPC分类号： G01R31/08 ,  G06F11/00 ,  H04J3/07

CPC分类号： H04J3/07 ,  H04J3/1629

摘要： A transmission apparatus exercises insertion control for inserting a client signal and a stuff byte into a payload area in a frame into which the client signal is to be mapped, and sends the frame after the insertion control. In addition, the transmission apparatus inserts the client signal or the stuff byte in columns of the frame into the payload area except a leading column.

摘要翻译： 发送装置进行插入控制，将客户端信号和填充字节插入到要映射客户端信号的帧中的有效载荷区域中，并且在插入控制之后发送帧。 此外，发送装置将客户端信号或填充字节插入到帧中的除了前导列之外的有效载荷区域中。

公开(公告)号：US20120251127A1

公开(公告)日：2012-10-04

申请号：US13365819

申请日：2012-02-03

申请人： Toshiaki OHKUBO ,  Toru Katagiri ,  Hiroyuki Honma ,  Hiromichi Makishima ,  Hiroyuki Kitajima

发明人： Toshiaki OHKUBO ,  Toru Katagiri ,  Hiroyuki Honma ,  Hiromichi Makishima ,  Hiroyuki Kitajima

IPC分类号： H04B10/04

CPC分类号： H04J3/1652

摘要： An apparatus for mapping multiple lower-speed signal transmission frames to a higher-speed signal transmission frame. The apparatus includes buffers configured to buffer the lower-speed signal transmission frames, determination units configured to determine frequency justification information for the lower-speed signal transmission frames, a barrel shifter configured to receive signals output from the buffers, and a controller configured to control the barrel shifter to map the lower-speed signal transmission frames to the higher-speed signal transmission frame based on external settings for the respective lower-speed signal transmission frames and the frequency justification information determined by the determination units. When the minimum unit of the lower-speed signal transmission frames is a channel, the number of the buffers and the number of the determination units correspond to the maximum number of channels that can be multiplexed in the higher-speed signal transmission frame.

摘要翻译： 一种用于将多个低速信号传输帧映射到更高速度的信号传输帧的装置。 该装置包括被配置为缓冲低速信号传输帧的缓冲器，被配置为确定低速信号传输帧的频率调整信息的确定单元，被配置为接收从缓冲器输出的信号的桶形移位器，以及被配置为控制 桶形移位器基于各个低速信号传输帧的外部设置和由确定单元确定的频率对齐信息将低速信号传输帧映射到较高速度的信号传输帧。 当低速信号传输帧的最小单位是信道时，缓冲器的数量和确定单元的数量对应于在高速信号传输帧中可以多路复用的最大信道数。

公开(公告)号：US20090232140A1

公开(公告)日：2009-09-17

申请号：US12403720

申请日：2009-03-13

申请人： Hiroyuki KITAJIMA ,  Hisaya Ogasawara ,  Atsushi Kitada

发明人： Hiroyuki KITAJIMA ,  Hisaya Ogasawara ,  Atsushi Kitada

IPC分类号： H04L12/56

CPC分类号： H04L49/552 ,  H04L49/1523 ,  H04L49/3072

摘要： A packet transmission apparatus includes a transmission unit dividing input data and transferring segments, which are obtained by adding sequence numbers to the respective pieces of the divided data, a switch unit transferring the segments to one of a plurality of reception units, and a reception unit reconstructing an original input packet from the plurality of segments that arrive from the switch units on the basis of the sequence numbers. The reception unit includes a packet buffer storing segments that arrive from the switch units, a determination unit determining, on the basis of the sequence number, whether the segment stored in the packet buffer is to be discarded; and a discard part reading the segment stored in the packet buffer in an order from the segment having an older sequence number and discarding the segment that is determined to be discarded.

摘要翻译： 分组传输装置包括：传输单元，用于将通过将各个分割数据的序列号相加得到的输入数据和传送段划分成将多个段传送到多个接收单元中的一个的接收单元;以及接收单元 基于序列号，重建从交换单元到达的多个段的原始输入分组。 接收单元包括存储从切换单元到达的分段的分组缓冲器，确定单元基于序列号确定是否要丢弃存储在分组缓冲器中的分段; 以及从具有较旧序列号的段以顺序读取存储在分组缓冲器中的段的丢弃部分，并且丢弃被确定为被丢弃的段。

公开(公告)号：US07498855B2

公开(公告)日：2009-03-03

申请号：US11193470

申请日：2005-08-01

申请人： Hiroyuki Kitajima

发明人： Hiroyuki Kitajima

IPC分类号： H03K3/02 ,  H03L7/00

CPC分类号： H03K17/223

摘要： A power-ON-clear circuit has a reset period when the power supply stops temporarily (or instantaneously) and then that power supply is restored. The power-ON-clear circuit 30 of a semiconductor integrated circuit 200 comprises: a capacitor C31 of which one end is connected to the external power-supply voltage Vcc1; an N-channel MOS transistor Q31 of which the drain is connected to the other end of the capacitor C31, the source is connected to the ground potential, and the gate is connected to the external power-supply voltage by way of a resistor R31; and an inverter INV31 that is connected to the connecting point between the capacitor C31 and MOS transistor Q31 in a stage connection, and is connected to the power supply between the internal power-supply voltage Vcc2 and the ground potential.

摘要翻译： 电源接通清除电路在电源暂停（或瞬时）停止时具有复位周期，然后恢复供电。 半导体集成电路200的上电清零电路30包括：一端与外部电源电压Vcc1连接的电容器C31; 漏极连接到电容器C31的另一端的N沟道MOS晶体管Q31，源极接地，栅极通过电阻R31连接到外部电源电压; 以及反相器INV31，其在级连接中连接到电容器C31和MOS晶体管Q31之间的连接点，并且在内部电源电压Vcc2和地电位之间连接到电源。

公开(公告)号：US06938125B2

公开(公告)日：2005-08-30

申请号：US10634919

申请日：2003-08-06

申请人： Akira Yamamoto ,  Takao Satoh ,  Shigeo Honma ,  Yoshihiro Asaka ,  Yoshiaki Kuwahara ,  Hiroyuki Kitajima

发明人： Akira Yamamoto ,  Takao Satoh ,  Shigeo Honma ,  Yoshihiro Asaka ,  Yoshiaki Kuwahara ,  Hiroyuki Kitajima

IPC分类号： G06F3/06 ,  G06F11/20 ,  G06F12/00 ,  G06F12/08 ,  G06F11/08 ,  G06F12/16

CPC分类号： G06F12/0866 ,  G06F3/061 ,  G06F3/0613 ,  G06F3/065 ,  G06F3/0659 ,  G06F3/0683 ,  G06F3/0689 ,  G06F11/2005 ,  G06F11/2007 ,  G06F11/2087 ,  G06F11/2089 ,  G06F12/0804 ,  G06F2206/1012

摘要： A disk storage system has a control unit having a plurality of external ports connectable to a mirrored disk including two disks to which write data is written. When the control unit receives two read requests issued from a processor to the disk unit group, a first read operation is performed to read data requested by the first read request from one of the disks and a second read operation is performed to read data requested by the second read request from the other one of the disks. Also, a first transferring operation is performed to transfer data read by the first read operation to one external port of the control unit and a second transferring operation is performed to transfer data read by the second read operation to another external port of the control unit. Further, the data read by the two read operations is transferred to the processor via the external ports.

摘要翻译： 磁盘存储系统具有控制单元，该控制单元具有可连接到镜像磁盘的多个外部端口，该多个外部端口包括写入数据的两个磁盘。 当控制单元接收到从处理器向盘单元组发出的两个读取请求时，执行第一读取操作以从其中一个盘读取由第一读取请求请求的数据，并且执行第二读取操作以读取由 来自另一个磁盘的第二个读取请求。 此外，执行第一传送操作以将通过第一读取操作读取的数据传送到控制单元的一个外部端口，并且执行第二传送操作以将通过第二读取操作读取的数据传送到控制单元的另一个外部端口。 此外，通过两个读取操作读取的数据经由外部端口传送到处理器。

公开(公告)号：US20050180227A1

公开(公告)日：2005-08-18

申请号：US11053957

申请日：2005-02-10

申请人： Hiroyuki Kitajima

发明人： Hiroyuki Kitajima

IPC分类号： H02M3/07 ,  G11C5/00 ,  G11C5/14

CPC分类号： G11C5/145

摘要： According to one aspect of the present invention, a booster circuit comprises a charge pump, a voltage supply section reducing a power supply voltage and supplying a voltage to the charge pump through an output metal-oxide-semiconductor (MOS) transistor of an operational amplifier and a drive MOS transistor maximizing a drive capacity of the output MOS transistor of the operational amplifier.

摘要翻译： 根据本发明的一个方面，一种升压电路包括一个电荷泵，一个电压供应部分，减小电源电压，并通过一个运算放大器的输出金属氧化物半导体（MOS）晶体管向电荷泵提供一个电压 以及使运算放大器的输出MOS晶体管的驱动能力最大化的驱动MOS晶体管。

公开(公告)号：US20050050267A1

公开(公告)日：2005-03-03

申请号：US10945882

申请日：2004-09-22

申请人： Akira Yamamoto ,  Hiroyuki Kitajima ,  Kouji Arai ,  Yoshihisa Kamo

发明人： Akira Yamamoto ,  Hiroyuki Kitajima ,  Kouji Arai ,  Yoshihisa Kamo

IPC分类号： G06F11/10 ,  G06F12/16

CPC分类号： G06F11/1076 ,  G06F2211/1009

摘要： When receiving a write request from a processor, a control unit checks the condition of existence (or the presence/absence) in a cache for information necessary for generation of an updated value of a parity record, receives write data and reports the completion of the write request to the processor. In asynchronism with the write request from the processor, the control unit performs a load process for that information among the information necessary for generation of the updated value of the parity record which may be prepared in asynchronism with the write request from the processor and a write after process for the updated value of the parity record.