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公开(公告)号：US08571073B2
公开(公告)日：2013-10-29
申请号：US13365819
申请日：2012-02-03
IPC分类号： H04J3/02
CPC分类号： H04J3/1652
摘要： An apparatus for mapping multiple lower-speed signal transmission frames to a higher-speed signal transmission frame. The apparatus includes buffers configured to buffer the lower-speed signal transmission frames, determination units configured to determine frequency justification information for the lower-speed signal transmission frames, a barrel shifter configured to receive signals output from the buffers, and a controller configured to control the barrel shifter to map the lower-speed signal transmission frames to the higher-speed signal transmission frame based on external settings for the respective lower-speed signal transmission frames and the frequency justification information determined by the determination units. When the minimum unit of the lower-speed signal transmission frames is a channel, the number of the buffers and the number of the determination units correspond to the maximum number of channels that can be multiplexed in the higher-speed signal transmission frame.
摘要翻译： 一种用于将多个低速信号传输帧映射到更高速度的信号传输帧的装置。 该装置包括被配置为缓冲低速信号传输帧的缓冲器，被配置为确定低速信号传输帧的频率调整信息的确定单元，被配置为接收从缓冲器输出的信号的桶形移位器，以及被配置为控制 桶形移位器基于各个低速信号传输帧的外部设置和由确定单元确定的频率对齐信息将低速信号传输帧映射到较高速度的信号传输帧。 当低速信号传输帧的最小单位是信道时，缓冲器的数量和确定单元的数量对应于在高速信号传输帧中可以多路复用的最大信道数。
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公开(公告)号：US20120251127A1
公开(公告)日：2012-10-04
申请号：US13365819
申请日：2012-02-03
IPC分类号： H04B10/04
CPC分类号： H04J3/1652
摘要： An apparatus for mapping multiple lower-speed signal transmission frames to a higher-speed signal transmission frame. The apparatus includes buffers configured to buffer the lower-speed signal transmission frames, determination units configured to determine frequency justification information for the lower-speed signal transmission frames, a barrel shifter configured to receive signals output from the buffers, and a controller configured to control the barrel shifter to map the lower-speed signal transmission frames to the higher-speed signal transmission frame based on external settings for the respective lower-speed signal transmission frames and the frequency justification information determined by the determination units. When the minimum unit of the lower-speed signal transmission frames is a channel, the number of the buffers and the number of the determination units correspond to the maximum number of channels that can be multiplexed in the higher-speed signal transmission frame.
摘要翻译： 一种用于将多个低速信号传输帧映射到更高速度的信号传输帧的装置。 该装置包括被配置为缓冲低速信号传输帧的缓冲器，被配置为确定低速信号传输帧的频率调整信息的确定单元，被配置为接收从缓冲器输出的信号的桶形移位器，以及被配置为控制 桶形移位器基于各个低速信号传输帧的外部设置和由确定单元确定的频率对齐信息将低速信号传输帧映射到较高速度的信号传输帧。 当低速信号传输帧的最小单位是信道时，缓冲器的数量和确定单元的数量对应于在高速信号传输帧中可以多路复用的最大信道数。
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公开(公告)号：US20130058643A1
公开(公告)日：2013-03-07
申请号：US13665146
申请日：2012-10-31
申请人： Hiroyuki HONMA , Toru Katagiri , Hiromichi Makishima , Masahiro Shioda , Hiroyuki Kitajima , Ichiro Yokokura
发明人： Hiroyuki HONMA , Toru Katagiri , Hiromichi Makishima , Masahiro Shioda , Hiroyuki Kitajima , Ichiro Yokokura
IPC分类号： H04B10/08
CPC分类号： H04J3/1652 , H04J2203/0058 , H04L43/0876
摘要： A data amount derivation apparatus includes: a first calculator configured to derive, for one series of parallelized mapping signals, amount of data in each frame period for a frame into which the parallelized mapping signals are mapped; and a second calculator configured to sum up amounts of data in N frame periods, where N is an integer, and to derive the resulting summation value as the amount of data to be mapped into the frame, each of the amounts of data in each of the frame periods being derived by the first calculator.
摘要翻译： 数据量导出装置包括：第一计算器，被配置为针对一系列并行映射信号，对并行映射信号映射到的帧的每个帧周期中的数据量; 以及第二计算器，被配置为对N个帧周期内的数据量进行相加，其中N是整数，并且导出所得到的求和值作为要映射到该帧中的数据量，每个数据量 帧周期由第一计算器导出。
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公开(公告)号：US08521176B2
公开(公告)日：2013-08-27
申请号：US13436796
申请日：2012-03-30
IPC分类号： H04B17/00
CPC分类号： H04B17/004 , H04B10/0799 , H04B10/50 , H04B17/20 , H04J3/07 , H04J3/1652
摘要： In a transmission apparatus, a comparison unit provides threshold values associated with an amount of data indicating a signal frequency, and compares an input parameter obtained by cumulatively adding a correction amount to the parameter with the threshold values. When the input parameter is within a range defined by the threshold values, a correction unit outputs a value of the input parameter. When the input parameter is out of the defined range, the correction unit outputs an associated one of the threshold values so as to eliminate an amount exceeding or falling short of the defined range, to thereby correct the input parameter. An addition unit detects the correction amount which is an amount of the immediately preceding value of the input parameter exceeding or falling short of the defined range, and cumulatively adds the correction amount to the input parameter used for the comparison of this time.
摘要翻译： 在发送装置中，比较单元提供与指示信号频率的数据量相关联的阈值，并将通过将该修正量累加到该参数而获得的输入参数与阈值进行比较。 当输入参数在由阈值定义的范围内时，校正单元输出输入参数的值。 当输入参数超出限定范围时，校正单元输出相关联的一个阈值，以便消除超过或超出限定范围的量，从而校正输入参数。 加法单元检测作为输入参数的紧接在前的值的量的校正量超过或者不超过限定范围，并且将校正量累加到用于此时间的比较的输入参数。
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公开(公告)号：US08767748B2
公开(公告)日：2014-07-01
申请号：US13220297
申请日：2011-08-29
CPC分类号： H04W72/0446 , H04B7/2628 , H04J3/07 , H04J3/1652 , H04W84/08
摘要： A signal distribution circuit includes: first to n-th input lines on which first to n-th signals are respectively input; first to (n−1)th selectors each of which selects one of two inputs under the control of a select signal; and a first output line on which the first signal is output and second to n-th output lines on which output signals of the first to (n−1)th selectors are respectively output, wherein: the first and second inputs of the first selector are supplied with the first signal and the second signal, respectively, the first and second inputs of the i-th selector (i is an integer between 2 and (n−1)) are supplied with the output signal of the (i−1)th selector and the (i+1)th signal, respectively, and any of the selectors, when selected by the select signal, selects the second input and, when not selected by the select signal, selects the first input.
摘要翻译： 信号分配电路包括：分别输入第一至第n信号的第一至第n输入线; 第一至第（n-1）个选择器，每个选择器在选择信号的控制下选择两个输入中的一个; 以及输出第一信号的第一输出线和分别输出第一至第（n-1）个选择器的输出信号的第二至第n输出线，其中：第一选择器的第一和第二输入 分别提供第一信号和第二信号，第i个选择器的第一和第二输入（i是2和（n-1）之间的整数）被提供有第（i-1）的输出信号 ）选择器和第（i + 1）个信号，并且当选择信号选择时，任何选择器选择第二输入，并且当未被选择信号选择时，选择第一输入。
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6.发明申请Circuit design apparatus, circuit design program, and circuit design method 审中-公开电路设计装置，电路设计程序及电路设计方法公开(公告)号：US20070143726A1
公开(公告)日：2007-06-21
申请号：US11384344
申请日：2006-03-21
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/78
摘要： There is provided a circuit design apparatus that performs logic design for realizing a reduction of power consumption and circuit simplification. A circuit design apparatus interprets RTL of a design target to perform structure analysis thereof (S2), estimates generation of a clock gating based on a result of the structure analysis, detects RTL description of an EN generation logic (S3), and detects the same EN generation logic (S4). The apparatus determines an insertion location of the clock gating circuit and reorganization of logical hierarchies based on the detected EN generation logic (S5), instructs logical hierarchy reorganization to be performed in logic synthesis (S8) and performs design change processing (S6). The apparatus performs logic synthesis based on RTL after design change and instruction of logical hierarchy reorganization (S10), and layouts a concrete circuit configuration (S12).
摘要翻译： 提供了一种电路设计装置，其执行逻辑设计以实现功率消耗的降低和电路简化。 电路设计装置解释设计目标的RTL以执行其结构分析（S 2），基于结构分析的结果估计时钟门控的产生，检测EN生成逻辑（S 3）的RTL描述，并且检测 相同的EN生成逻辑（S 4）。 该装置基于检测到的EN生成逻辑（S 5）确定时钟选通电路的插入位置和逻辑层次的重新组合，指示在逻辑合成中执行逻辑层次重组（S 8），并进行设计变更处理（S 6 ）。 该设备在设计改变和逻辑层次重组指令之后，基于RTL执行逻辑综合（S10），并布置了具体的电路配置（S12）。
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7.发明授权Cell bridge apparatus and cell bridging method as well as information transmission system having cell bridge apparatus 失效单元桥装置和单元桥接方法以及具有单元桥装置的信息传输系统公开(公告)号：US06788684B2
公开(公告)日：2004-09-07
申请号：US09201106
申请日：1998-11-30
申请人： Hiromichi Makishima , Yuji Obana , Hiroyuki Asano , Toshiaki Ookubo , Hideo Abe
发明人： Hiromichi Makishima , Yuji Obana , Hiroyuki Asano , Toshiaki Ookubo , Hideo Abe
IPC分类号： H04L1228
CPC分类号： H04L12/4625
摘要： An ATM cell bridge apparatus and a cell bridging method as well as an information transmission system having a cell bridge apparatus by which a cell can be outputted in accordance with a priority degree even during multicast processing. The ATM cell bridge apparatus includes a buffer unit for storing cell data of input cells, a buffer control unit for controlling writing and reading out of the cell data into and from the buffer unit, a cell production control unit for managing multicast information of the cell data read out from the buffer unit by the buffer control unit and producing a cell to be outputted from header information of the cell data, and a cell outputting unit for outputting the cell produced by the cell production control unit and issuing a cell data readout request to the buffer control unit.
摘要翻译： ATM信元网桥装置和信元桥接方法以及信息传输系统，具有可以在多播处理期间根据优先级顺序输出信元的单元桥接装置。 ATM单元桥接装置包括：存储输入单元的单元数据的缓冲单元;缓冲单元控制单元数据写入和读出的缓冲器控制单元;单元生成控制单元，用于管理单元的组播信息 由缓冲器单元从缓冲器单元读出的数据，并产生要从单元数据的标题信息输出的单元;以及单元输出单元，用于输出由单元生成控制单元产生的单元并发出单元数据读出请求 到缓冲器控制单元。
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8.发明授权Failure detection improvement apparatus, failure detection improvement program, failure detection improvement method 失效故障检测改进装置，故障检测改进程序，故障检测改进方法公开(公告)号：US07467362B2
公开(公告)日：2008-12-16
申请号：US11167281
申请日：2005-06-28
IPC分类号： G06F17/50
CPC分类号： G06F11/263
摘要： A failure detection improvement apparatus that modifies a net list comprises; a net list input section to which the net list is input; a circuit modification section that adds an observation FF to an appropriate location on the net list; and a net list output section that outputs the net list that has been modified by the circuit modification section.
摘要翻译： 修改网表的故障检测改善装置包括： 网络列表输入的网络列表输入部分; 将观察FF添加到网络列表上的适当位置的电路修改部分; 以及网表输出部，其输出由电路修改部修改的网表。
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公开(公告)号：US20100238954A1
公开(公告)日：2010-09-23
申请号：US12697245
申请日：2010-01-30
IPC分类号： H04J3/22
CPC分类号： H04J3/0623
摘要： A transmitting apparatus includes a detecting unit that detects deviation and balance relative to a specified bit rate of a frame signal input at a constant bit rate; a dividing unit that reads at constant intervals from a buffer storing the frame signal and outputs a signal divided into a plurality of segments having a predetermined data length; and a correcting unit that, based on the deviation and balance detected by the detecting unit, corrects the data length for the division by the dividing unit.
摘要翻译： 发送装置包括检测单元，其检测相对于以恒定比特率输入的帧信号的指定比特率的偏差和平衡; 分割单元，从存储帧信号的缓冲器以恒定的间隔读取，并输出分割成具有预定数据长度的多个段的信号; 以及校正单元，其基于由所述检测单元检测到的偏差和平衡来校正由所述分割单元划分的数据长度。
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公开(公告)号：US08300660B2
公开(公告)日：2012-10-30
申请号：US12697245
申请日：2010-01-30
IPC分类号： H04J3/22
CPC分类号： H04J3/0623
摘要： A transmitting apparatus includes a detecting unit that detects deviation and balance relative to a specified bit rate of a frame signal input at a constant bit rate; a dividing unit that reads at constant intervals from a buffer storing the frame signal and outputs a signal divided into a plurality of segments having a predetermined data length; and a correcting unit that, based on the deviation and balance detected by the detecting unit, corrects the data length for the division by the dividing unit.
摘要翻译： 发送装置包括检测单元，其检测相对于以恒定比特率输入的帧信号的指定比特率的偏差和平衡; 分割单元，从存储帧信号的缓冲器以恒定的间隔读取，并输出分割成具有预定数据长度的多个段的信号; 以及校正单元，其基于由所述检测单元检测到的偏差和平衡来校正由所述分割单元划分的数据长度。
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