公开(公告)号：US20140063663A1

公开(公告)日：2014-03-06

申请号：US13598194

申请日：2012-08-29

申请人： Federico Agustin ALTOLAGUIRRE ,  Ming-Dou Ker ,  Ryan Hsin-Chin Jiang

发明人： Federico Agustin ALTOLAGUIRRE ,  Ming-Dou Ker ,  Ryan Hsin-Chin Jiang

IPC分类号： H02H9/04

CPC分类号： H02H9/046 ,  H01L2924/0002 ,  H01L2924/00

摘要： A power-rail ESD clamp circuit with a silicon controlled rectifier and a control module is provided. The silicon controlled rectifier is connected to a high voltage level and a low voltage level for bearing a current flow. The control module is connected to the silicon controlled rectifier in parallel, and includes a PMOS, a NMOS, at least one output diode, a resistor and a conducting string. The silicon controlled rectifier is a P+ or N+ triggered silicon controlled rectifier. By employing the novel power-rail ESD clamp circuit, it is extraordinarily advantageous of reducing both a standby leakage current and layout area while implementation.

摘要翻译： 提供了具有可控硅整流器和控制模块的电力轨道ESD钳位电路。 可控硅整流器连接到高电压电平和低电压电平以承受电流。 控制模块并联连接到可控硅整流器，并且包括PMOS，NMOS，至少一个输出二极管，电阻器和导电串。 可控硅整流器是P +或N +触发的可控硅整流器。 通过采用新型的电源轨ESD钳位电路，在实现时减少备用漏电流和布局面积是非常有利的。

公开(公告)号：US08169000B2

公开(公告)日：2012-05-01

申请号：US12836785

申请日：2010-07-15

申请人： Che-Hao Chuang ,  Kun-Hsien Lin ,  Ryan Hsin-Chin Jiang

发明人： Che-Hao Chuang ,  Kun-Hsien Lin ,  Ryan Hsin-Chin Jiang

IPC分类号： H01L23/62

CPC分类号： H01L27/0255

摘要： A lateral transient voltage suppressor with ultra low capacitance is disclosed. The suppressor comprises a first conductivity type substrate and at least one diode cascade structure arranged in the first conductivity type substrate. The cascade structure further comprises at least one second conductivity type lightly doped well and at least one first conductivity type lightly doped well, wherein there are two heavily doped areas arranged in the second conductivity type lightly doped well and the first conductivity type lightly doped well. The cascade structure neighbors a second conductivity type well, wherein there are three heavily doped areas arranged in the second conductivity type well. The suppressor further comprises a plurality of deep isolation trenches arranged in the first conductivity type substrate and having a depth greater than depths of the second conductivity type lightly doped well, the second conductivity type well and the first conductivity type lightly doped well. Each doped well is isolated by trenches.

摘要翻译： 公开了具有超低电容的横向瞬态电压抑制器。 抑制器包括第一导电型衬底和布置在第一导电类型衬底中的至少一个二极管级联结构。 级联结构还包括至少一个第二导电类型轻掺杂阱和至少一个第一导电类型轻掺杂阱，其中存在布置在第二导电类型轻掺杂阱和第一导电类型轻掺杂阱中的两个重掺杂区。 级联结构邻近第二导电类型阱，其中存在布置在第二导电类型阱中的三个重掺杂区域。 抑制器还包括布置在第一导电类型衬底中并且具有大于第二导电类型轻掺杂阱的深度的深度的多个深隔离沟槽，第二导电类型阱和第一导电类型轻掺杂阱。 每个掺杂的阱由沟槽隔离。

公开(公告)号：US20120068299A1

公开(公告)日：2012-03-22

申请号：US12888151

申请日：2010-09-22

申请人： Kun-Hsien Lin ,  Che-Hao Chuang ,  Ryan Hsin-Chin Jiang

发明人： Kun-Hsien Lin ,  Che-Hao Chuang ,  Ryan Hsin-Chin Jiang

IPC分类号： H01L23/60

CPC分类号： H01L29/8613 ,  H01L27/0255 ,  H01L27/0259 ,  H01L29/866

摘要： The present invention relates a transient voltage suppressor (TVS) for directional ESD protection. The TVS includes: a conductivity type substrate; a first type lightly doped region, having a first type heavily doped region arranged therein; a second type lightly doped region, having a second type heavily doped region and a third type heavily doped region arranged therein; a third type lightly doped region, having a fourth type heavily doped region arranged therein; a plurality of closed isolation trenches, arranged on the conductivity type substrate, wherein at least one of the plurality of closed isolation trenches is neighbored one of the type lightly doped regions; and a first pin. Accordingly, the TVS of present invention may adaptively provide effective ESD protection under positive and negative ESD stresses, improve the efficiency of ESD protection within the limited layout area.

摘要翻译： 本发明涉及用于定向ESD保护的瞬态电压抑制器（TVS）。 TVS包括：导电型基板; 第一类型轻掺杂区域，其中布置有第一类型重掺杂区域; 具有第二类型重掺杂区域和布置在其中的第三类型重掺杂区域的第二类型轻掺杂区域; 第三类型轻掺杂区域，其中布置有第四类型重掺杂区域; 多个封闭的隔离沟槽，布置在所述导电型衬底上，其中所述多个闭合隔离沟槽中的至少一个与所述轻掺杂区域中的一个相邻; 和第一个引脚。 因此，本发明的TVS可以在正和负ESD应力下自适应地提供有效的ESD保护，从而在有限的布局区域内提高ESD保护的效率。

公开(公告)号：US20120012974A1

公开(公告)日：2012-01-19

申请号：US12837128

申请日：2010-07-15

申请人： Che-Hao CHUANG ,  Kun-Hsien Lin ,  Ryan Hsin-Chin Jiang

发明人： Che-Hao CHUANG ,  Kun-Hsien Lin ,  Ryan Hsin-Chin Jiang

IPC分类号： H01L29/06

CPC分类号： H01L27/0255

摘要： A lateral transient voltage suppressor for low-voltage applications is disclosed. The suppressor comprises an N-type heavily doped substrate and at least two clamp diode structures horizontally arranged in the N-type heavily doped substrate. Each clamp diode structure further comprises a clamp well arranged in the N-type heavily doped substrate and having a first heavily doped area and a second heavily doped area. The first and second heavily doped areas respectively belong to opposite types. There is a plurality of deep isolation trenches arranged in the N-type heavily doped substrate and having a depth greater than depth of the clamp well. The deep isolation trenches can separate each clamp well. The present invention avoids the huge leakage current to be suitable for low-voltage application.

摘要翻译： 公开了一种用于低电压应用的横向瞬态电压抑制器。 抑制器包括N型重掺杂衬底和水平地布置在N型重掺杂衬底中的至少两个钳位二极管结构。 每个钳位二极管结构还包括在N型重掺杂衬底中布置的具有第一重掺杂区域和第二重掺杂区域的钳位阱。 第一和第二重掺杂区域分别属于相反的类型。 在N型重掺杂衬底中布置有多个深的隔离沟槽，其深度大于夹具阱的深度。 深的隔离沟槽可以很好地分离每个夹具。 本发明避免了巨大的漏电流适合于低电压应用。

公开(公告)号：US20120012973A1

公开(公告)日：2012-01-19

申请号：US12836785

申请日：2010-07-15

申请人： Che-Hao Chuang ,  Kun-Hsien Lin ,  Ryan Hsin-Chin Jiang

发明人： Che-Hao Chuang ,  Kun-Hsien Lin ,  Ryan Hsin-Chin Jiang

IPC分类号： H01L29/06

CPC分类号： H01L27/0255

摘要： A lateral transient voltage suppressor with ultra low capacitance is disclosed. The suppressor comprises a first type substrate and at least one diode cascade structure arranged in the first type substrate. The cascade structure further comprises at least one second type lightly doped well and at least one first type lightly doped well, wherein there are two heavily doped areas arranged in the second type lightly doped well and the first type lightly doped well. The cascade structure neighbors a second type well, wherein there are three heavily doped areas arranged in the second type well. The suppressor further comprises a plurality of deep isolation trenches arranged in the first type substrate and having a depth greater than depths of the second type lightly doped well, the second type well and the first type lightly doped well. Each doped well is isolated by trenches.

摘要翻译： 公开了具有超低电容的横向瞬态电压抑制器。 抑制器包括第一类型衬底和布置在第一类型衬底中的至少一个二极管级联结构。 级联结构还包括至少一个第二类型轻掺杂阱和至少一个第一类型轻掺杂阱，其中在第二类型轻掺杂阱和第一类型轻掺杂阱中布置有两个重掺杂区。 级联结构邻近第二类型井，其中在第二类井中布置有三个重掺杂区域。 抑制器还包括布置在第一类型衬底中并且具有大于第二类型轻掺杂阱，第二类型阱和第一类型轻掺杂阱的深度的深度的多个深隔离沟槽。 每个掺杂的阱由沟槽隔离。

公开(公告)号：US08049247B2

公开(公告)日：2011-11-01

申请号：US12113410

申请日：2008-05-01

申请人： Tang-Kuei Tseng ,  Che-Hao Chuang ,  Ryan Hsin-Chin Jiang ,  Ming-Dou Ker

发明人： Tang-Kuei Tseng ,  Che-Hao Chuang ,  Ryan Hsin-Chin Jiang ,  Ming-Dou Ker

IPC分类号： H01L29/747

CPC分类号： H01L29/747 ,  H01L27/0262 ,  H01L29/87

摘要： The present invention discloses an asymmetric bidirectional silicon-controlled rectifier, which comprises: a second conduction type substrate; a first conduction type undoped epitaxial layer formed on the substrate; a first well and a second well both formed inside the undoped epitaxial layer and separated by a portion of the undoped epitaxial layer; a first buried layer formed in a junction between the first well and the substrate; a second buried layer formed in a junction between the second well and the substrate; a first and a second semiconductor area with opposite conduction type both formed inside the first well; a third and a fourth semiconductor area with opposite conduction type both formed inside the second well, wherein the first and second semiconductor areas are connected to the anode of the silicon-controlled rectifier, and the third and fourth semiconductor areas are connected to the cathode of the silicon-controlled rectifier.

摘要翻译： 本发明公开了一种不对称双向硅控整流器，其包括：第二导电型衬底; 形成在基板上的第一导电型未掺杂外延层; 第一阱和第二阱都形成在未掺杂的外延层内部并由未掺杂的外延层的一部分分离; 第一掩埋层，形成在所述第一阱和所述衬底之间的接合处; 第二掩埋层，形成在所述第二阱和所述衬底之间的接合处; 在第一阱内形成具有相反导电类型的第一和第二半导体区域; 具有相反导电类型的第三和第四半导体区域都形成在第二阱内部，其中第一和第二半导体区域连接到可控硅整流器的阳极，并且第三和第四半导体区域连接到 硅控整流器。

公开(公告)号：US07705404B2

公开(公告)日：2010-04-27

申请号：US11613193

申请日：2006-12-20

申请人： Ming-Dou Ker ,  Jia-Huei Chen ,  Ryan Hsin-Chin Jiang

发明人： Ming-Dou Ker ,  Jia-Huei Chen ,  Ryan Hsin-Chin Jiang

IPC分类号： H01L23/62

CPC分类号： H01L27/027 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrostatic discharge (ESD) protection device and a layout thereof are provided. A bias conducting wire is mainly used to couple each base of a plurality of parasitic transistors inside ESD elements together, in order to simultaneously trigger all the parasitic transistors to bypass the ESD current, avoid the elements of a core circuit being damaged, and solve the non-uniform problem of bypassing the ESD current when ESD occurs. Furthermore, in the ESD protection layout, it only needs to add another doped region on a substrate neighboring to, but not contacting, doped regions of the ESD protection elements and use contacts to connect the added doped region, so as to couple each base of the parasitic transistors together without requiring for additional layout area.

摘要翻译： 提供静电放电（ESD）保护装置及其布局。 偏置导线主要用于将ESD元件内的多个寄生晶体管的每个基极耦合在一起，以便同时触发所有寄生晶体管绕过ESD电流，避免核心电路的元件被损坏，并解决 当ESD发生时绕过ESD电流的非均匀问题。 此外，在ESD保护布局中，仅需要在与ESD保护元件的掺杂区域相邻但不接触的衬底上添加另一个掺杂区域，并使用触点来连接所添加的掺杂区域，以便将 寄生晶体管一起而不需要额外的布局区域。

公开(公告)号：US07663853B2

公开(公告)日：2010-02-16

申请号：US11618674

申请日：2006-12-29

申请人： Ming-Dou Ker ,  Jang-Jie Peng ,  Hsin-Chin Jiang

发明人： Ming-Dou Ker ,  Jang-Jie Peng ,  Hsin-Chin Jiang

IPC分类号： H02H7/00

CPC分类号： H01L27/0248 ,  H03K17/0822

摘要： An on-chip latch-up protection circuit. The lath-up protection circuit includes a core circuit, a power switch, and a current extractor. The power switch controls major current flowing through the core circuit. The current extractor detects amplitude of the major current. The power switch, the core circuit and the current extractor are coupled in series between a relatively-high power line and a relatively-low power line. When the major current surpasses a predetermined amplitude, the power switch is turned off, causing latch-up stops.

摘要翻译： 一个片内闭锁保护电路。 上拉保护电路包括核心电路，电源开关和电流提取器。 电源开关控制流经核心电路的大电流。 当前提取器检测主电流的幅度。 电源开关，核心电路和电流提取器串联在相对较高的电力线和相对低的电力线之间。 当主电流超过预定幅度时，电源开关被关闭，导致闭锁停止。

公开(公告)号：US20090296293A1

公开(公告)日：2009-12-03

申请号：US12129230

申请日：2008-05-29

申请人： Ming Dou KER ,  Yuan Wen HSIAO ,  Hsin Chin JIANG

发明人： Ming Dou KER ,  Yuan Wen HSIAO ,  Hsin Chin JIANG

IPC分类号： H02H9/00

CPC分类号： H01L27/0251 ,  H03F1/523 ,  H03F3/45183

摘要： An ESD protection circuit for a differential I/O pair is provided. The circuit includes an ESD detection circuit, a discharge device, and four diodes. The first diode is coupled between the first I/O pin and the discharge device in a forward direction toward the discharge device. The second diode is coupled between the second I/O pin and the discharge device in a forward direction toward the second I/O pin. The third diode is coupled between the discharge device and the positive power line in a forward direction toward the positive power line. The fourth diode is coupled between the discharge device and the negative power line in a forward direction toward the discharge device. Via an output end, the ESD detection circuit triggers the discharge device during ESD events.

摘要翻译： 提供了用于差分I / O对的ESD保护电路。 该电路包括ESD检测电路，放电装置和四个二极管。 第一二极管在朝向放电装置的正向方向上在第一I / O引脚和放电装置之间耦合。 第二二极管在第二I / O引脚和放电装置之间朝向第二I / O引脚向前方连接。 第三二极管朝着正电力线向前方连接在放电装置和正电力线之间。 第四二极管在放电装置和负电源线之间朝向放电装置向前方连接。 通过输出端，ESD检测电路在ESD事件期间触发放电装置。

公开(公告)号：US07253999B2

公开(公告)日：2007-08-07

申请号：US10446049

申请日：2003-05-28

申请人： Ming-Dou Ker ,  Jeng-Jie Peng ,  Hsin-Chin Jiang

发明人： Ming-Dou Ker ,  Jeng-Jie Peng ,  Hsin-Chin Jiang

IPC分类号： H02H9/00

CPC分类号： H01L27/0248 ,  H03K17/0822

摘要： An on-chip latch-up protection circuit. The lath-up protection circuit includes a core circuit, a power switch, and a current extractor. The power switch controls major current flowing through the core circuit. The current extractor detects amplitude of the major current. The power switch, the core circuit and the current extractor are coupled in series between a relatively-high power line and a relatively-low power line. When the major current surpasses a predetermined amplitude, the power switch is turned off, causing latch-up stops.

摘要翻译： 一个片内闭锁保护电路。 上拉保护电路包括核心电路，电源开关和电流提取器。 电源开关控制流经核心电路的大电流。 当前提取器检测主电流的幅度。 电源开关，核心电路和电流提取器串联在相对较高的电力线和相对低的电力线之间。 当主电流超过预定幅度时，电源开关被关闭，导致闭锁停止。