公开(公告)号：US20130153957A1

公开(公告)日：2013-06-20

申请号：US13331241

申请日：2011-12-20

申请人： Kun-Hsien Lin ,  Che-Hao Chuang ,  Ryan Hsin-Chin Jiang

发明人： Kun-Hsien Lin ,  Che-Hao Chuang ,  Ryan Hsin-Chin Jiang

IPC分类号： H01L29/73

CPC分类号： H01L27/0262 ,  H01L29/861

摘要： A silicon-controlled-rectifier (SCR) with adjustable holding voltage is disclosed, which comprises a heavily doped semiconductor layer and an epitaxial layer formed on the heavily doped semiconductor layer. A first N-well having a first P-heavily doped area is formed in the epitaxial layer. A second N-well or a first P-well is formed in the epitaxial layer. When the second N-well is formed in the epitaxial layer, a P-doped area is located between the first N-well and the second N-well. Besides, a first N-heavily doped area is formed in the second N-well or the first P-well. At least one deep isolation trench is formed in the epitaxial layer and located between the first P-heavily doped area and the first N-heavily doped area. A distance between the deep isolation trench and the heavily doped semiconductor layer is larger than zero.

摘要翻译： 公开了具有可调保持电压的硅控整流器（SCR），其包括在重掺杂半导体层上形成的重掺杂半导体层和外延层。 在外延层中形成具有第一P重掺杂区的第一N阱。 在外延层中形成第二N阱或第一P阱。 当第二N阱形成在外延层中时，P掺杂区域位于第一N阱和第二N阱之间。 此外，在第二N阱或第一P阱中形成第一N重掺杂区。 在外延层中形成至少一个深的隔离沟槽，并且位于第一P重掺杂区域和第一N重掺杂区域之间。 深隔离沟槽和重掺杂半导体层之间的距离大于零。

公开(公告)号：US20130127007A1

公开(公告)日：2013-05-23

申请号：US13303946

申请日：2011-11-23

申请人： Che-Hao Chuang ,  Kun-Hsien Lin ,  Ryan Hsin-Chin Jiang

发明人： Che-Hao Chuang ,  Kun-Hsien Lin ,  Ryan Hsin-Chin Jiang

IPC分类号： H01L29/06

CPC分类号： H01L27/0296 ,  H01L29/8613 ,  H01L29/866

摘要： A transient voltage suppressor without leakage current is disclosed, which comprises a P-substrate. There is an N-type epitaxial layer formed on the P-substrate, and a first N-heavily doped area, a first P-heavily doped area, an electrostatic discharge (ESD) device and at least one deep isolation trench are formed in the N-epitaxial layer. A first N-buried area is formed in the bottom of the N-epitaxial layer to neighbor the P-substrate and located below the first N-heavily doped area and the first P-heavily doped area. The ESD device is coupled to the first N-heavily doped area. The deep isolation trench is not only adjacent to the first N-heavily doped area, but has a depth greater than a depth of the first N-buried area, thereby separating the first N-buried area and the ESD device.

摘要翻译： 公开了一种无泄漏电流的瞬态电压抑制器，其包括P型衬底。 在P基板上形成有N型外延层，在第一N重掺杂区，第一P重掺杂区，静电放电（ESD）器件和至少一个深隔离沟槽中形成第一N重掺杂区， N外延层。 在N外延层的底部形成第一N区，以邻近P衬底并且位于第一N重掺杂区和第一P重掺杂区的下方。 ESD器件耦合到第一N重掺杂区域。 深隔离沟槽不仅与第一N重掺杂区相邻，而且具有大于第一N埋入区深度的深度，从而分离第一N埋区和ESD器。

公开(公告)号：US20120241903A1

公开(公告)日：2012-09-27

申请号：US13072138

申请日：2011-03-25

申请人： Yu-Shu SHEN ,  Kun-Hsien Lin ,  Che-Hao Chuang ,  Ryan Hsin-Chin Jiang

发明人： Yu-Shu SHEN ,  Kun-Hsien Lin ,  Che-Hao Chuang ,  Ryan Hsin-Chin Jiang

IPC分类号： H01L29/66

CPC分类号： H01L27/0255 ,  H01L29/861

摘要： A low capacitance transient voltage suppressor is disclosed. The suppressor comprises an N-type heavily doped substrate and an epitaxial layer formed on the substrate. At least one steering diode structure formed in the epitaxial layer comprises a diode lightly doped well and a first P-type lightly doped well, wherein a P-type heavily doped area is formed in the diode lightly doped well and a first N-type heavily doped area and a second P-type heavily doped area are formed in the first P-type lightly doped well. A second P-type lightly doped well having two N-type heavily doped areas is formed in the epitaxial layer. In addition, an N-type heavily doped well and at least one deep isolation trench are formed in the epitaxial layer, wherein the trench has a depth greater than or equal to depths of all the doped wells, so as to separate at least one doped well.

摘要翻译： 公开了一种低电容瞬态电压抑制器。 抑制器包括N型重掺杂衬底和形成在衬底上的外延层。 形成在外延层中的至少一个转向二极管结构包括二极管轻掺杂阱和第一P型轻掺杂阱，其中在二极管轻掺杂阱中形成P型重掺杂区，并且第一N型重掺杂阱 在第一P型轻掺杂阱中形成掺杂区域和第二P型重掺杂区域。 在外延层中形成具有两个N型重掺杂区的第二P型轻掺杂阱。 此外，在外延层中形成N型重掺杂阱和至少一个深隔离沟槽，其中沟槽的深度大于或等于所有掺杂阱的深度，以便分离至少一个掺杂的 好。

公开(公告)号：US20120014027A1

公开(公告)日：2012-01-19

申请号：US12836745

申请日：2010-07-15

申请人： Kun-Hsien LIN ,  Che-Hao Chuang ,  Ryan Hsin-Chin Jiang

发明人： Kun-Hsien LIN ,  Che-Hao Chuang ,  Ryan Hsin-Chin Jiang

IPC分类号： H02H3/22

CPC分类号： H02H9/046 ,  H05K1/0259

摘要： A transient voltage suppressor (TVS) for multiple pin assignments is disclosed. The suppressor comprises at least two cascade-diode circuits in parallel to each other and an electrostatic-discharge clamp element in parallel to each cascade-diode circuit and connected with a low voltage. One cascade-diode circuit is connected with a high voltage, and the other cascade-diode circuits are respectively connected with I/O pins. Each cascade-diode circuit further comprises a first diode and a second diode cascaded to the first diode, wherein a node between the first diode and the second diode is connected with the high voltage or the one I/O pin. The design of the present invention can meet several bounding requirements. It is flexible different pin assignments of TVS parts.

摘要翻译： 公开了一种用于多个引脚分配的瞬态电压抑制器（TVS）。 抑制器包括彼此并联的至少两个级联二极管电路和与每个级联二极管电路并联并与低电压连接的静电放电钳位元件。 一个级联二极管电路与高电压连接，其他级联二极管电路分别与I / O引脚相连。 每个级联二极管电路还包括级联到第一二极管的第一二极管和第二二极管，其中第一二极管和第二二极管之间的节点与高电压或一个I / O引脚连接。 本发明的设计可以满足多个限制要求。 它是TVS零件的灵活不同的引脚分配。

公开(公告)号：US07652511B2

公开(公告)日：2010-01-26

申请号：US12015395

申请日：2008-01-16

申请人： Che-Hao Chuang ,  Tang-Kuei Tseng ,  Ryan Hsin-Chin Jiang

发明人： Che-Hao Chuang ,  Tang-Kuei Tseng ,  Ryan Hsin-Chin Jiang

IPC分类号： H03K3/00

CPC分类号： H03K5/04 ,  H03K17/166 ,  H03K19/00361 ,  H04L25/0286

摘要： The present invention proposed a slew-rate control circuitry without the use of external components such as amplifiers. Therefore slew-rate control circuitry of the present invention not only provides an IC with build-in slew-rate control, but also reduces number of transistors used externally which will increase gate-oxide reliability of the IC. The slew-rate control circuitry of the present invention is primarily comprised by an output buffer and feedback circuitry, the output buffer mainly consisted four transistors and depends on output of the IC, these four transistors will interact with each other to control the slew-rate of IC output. Additional feedback circuitry and gate-tracking circuitry are also disclosed to enhance the performance of the slew-rate control circuitry.

摘要翻译： 本发明提出了一种不使用放大器等外部元件的压摆率控制电路。 因此，本发明的压摆率控制电路不仅提供具有内置转换速率控制的IC，而且还减少外部使用的晶体管的数量，这将增加IC的栅极氧化可靠性。 本发明的转换速率控制电路主要由输出缓冲器和反馈电路组成，输出缓冲器主要由四个晶体管组成，并依赖于IC的输出，这四个晶体管将相互交互以控制转换速率 的IC输出。 还公开了附加的反馈电路和栅极跟踪电路，以增强转换速率控制电路的性能。

公开(公告)号：US07525159B2

公开(公告)日：2009-04-28

申请号：US11768785

申请日：2007-06-26

申请人： Ming-Dou Ker ,  Che-Hao Chuang

发明人： Ming-Dou Ker ,  Che-Hao Chuang

IPC分类号： H01L23/62 ,  H01L21/332

CPC分类号： H01L27/0266

摘要： A semiconductor device suitable for applications in an electrostatic discharge (ESD) protection circuit, including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, and a first doped region formed in the second well, wherein the first well, the second well, and the first doped region collectively form a parasitic bipolar junction transistor (BJT), and wherein the first well is the collector of the BJT, the second well is the base of the BJT, and the first doped region is the emitter of the BJT.

摘要翻译： 一种适用于静电放电（ESD）保护电路的半导体器件，包括半导体衬底，在衬底中形成的第一阱，在衬底中形成的第二阱以及形成在第二阱中的第一掺杂区，其中， 第一阱，第二阱和第一掺杂区域共同形成寄生双极结型晶体管（BJT），其中第一阱是BJT的集电极，第二阱是BJT的基极，第一掺杂区域 是BJT的发射器。

公开(公告)号：US07504861B2

公开(公告)日：2009-03-17

申请号：US10871348

申请日：2004-06-21

申请人： Che-Hao Chuang ,  Ming-Dou Ker

发明人： Che-Hao Chuang ,  Ming-Dou Ker

IPC分类号： H03K19/0175

CPC分类号： H03K19/00361 ,  H03K19/0013 ,  H03K19/018521

摘要： A mixed-voltage buffer circuit coupled between a first circuit operative at a first power supply voltage and a second circuit operative at a second power supply voltage. The buffer circuit is connectable to the second power supply voltage and a third power supply voltage and includes an input circuit coupled to the first circuit through a first node and to the second circuit through a second node. The input circuit includes a first part coupled to the first node and an inverter coupled to the second node. The first part provides a signal having a voltage level approximately equal to the third power supply voltage to the inverter in response to a first signal on the first node, and provides a signal having a voltage level approximately equal to the second power supply voltage to the inverter in response to a second signal on the first node.

摘要翻译： 耦合在以第一电源电压工作的第一电路和以第二电源电压工作的第二电路的混合电压缓冲电路。 缓冲电路可连接到第二电源电压和第三电源电压，并且包括通过第一节点耦合到第一电路的输入电路，并且通过第二节点连接到第二电路。 输入电路包括耦合到第一节点的第一部分和耦合到第二节点的逆变器。 第一部分响应于第一节点上的第一信号，向逆变器提供具有近似等于第三电源电压的电压电平的信号，并且将具有近似等于第二电源电压的电压电平的信号提供给 响应于第一个节点上的第二个信号。

公开(公告)号：US20090032837A1

公开(公告)日：2009-02-05

申请号：US12113410

申请日：2008-05-01

申请人： Tang-Kuei Tseng ,  Che-Hao Chuang ,  Ryan Hsin-Chin Jiang ,  Ming-Dou Ker

发明人： Tang-Kuei Tseng ,  Che-Hao Chuang ,  Ryan Hsin-Chin Jiang ,  Ming-Dou Ker

IPC分类号： H01L29/747

CPC分类号： H01L29/747 ,  H01L27/0262 ,  H01L29/87

摘要： The present invention discloses an asymmetric bidirectional silicon-controlled rectifier, which comprises: a second conduction type substrate; a first conduction type undoped epitaxial layer formed on the substrate; a first well and a second well both formed inside the undoped epitaxial layer and separated by a portion of the undoped epitaxial layer; a first buried layer formed in a junction between the first well and the substrate; a second buried layer formed in a junction between the second well and the substrate; a first and a second semiconductor area with opposite conduction type both formed inside the first well; a third and a fourth semiconductor area with opposite conduction type both formed inside the second well, wherein the first and second semiconductor areas are connected to the anode of the silicon-controlled rectifier, and the third and fourth semiconductor areas are connected to the cathode of the silicon-controlled rectifier.

摘要翻译： 本发明公开了一种不对称双向硅控整流器，其包括：第二导电型衬底; 形成在基板上的第一导电型未掺杂外延层; 第一阱和第二阱都形成在未掺杂的外延层内部并由未掺杂的外延层的一部分分离; 第一掩埋层，形成在所述第一阱和所述衬底之间的接合处; 第二掩埋层，形成在所述第二阱和所述衬底之间的接合处; 在第一阱内形成具有相反导电类型的第一和第二半导体区域; 具有相反导电类型的第三和第四半导体区域都形成在第二阱内部，其中第一和第二半导体区域连接到可控硅整流器的阳极，并且第三和第四半导体区域连接到 硅控整流器。

公开(公告)号：US20080044969A1

公开(公告)日：2008-02-21

申请号：US11768814

申请日：2007-06-26

申请人： Ming-Dou Ker ,  Che-Hao Chuang

发明人： Ming-Dou Ker ,  Che-Hao Chuang

IPC分类号： H01L21/331 ,  H01L21/8222

CPC分类号： H01L27/0266

摘要： A semiconductor device suitable for applications in an electrostatic discharge (ESD) protection circuit, including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, and a first doped region formed in the second well, wherein the first well, the second well, and the first doped region collectively form a parasitic bipolar junction transistor (BJT), and wherein the first well is the collector of the BJT, the second well is the base of the BJT, and the first doped region is the emitter of the BJT.

摘要翻译： 一种适用于静电放电（ESD）保护电路的半导体器件，包括半导体衬底，在衬底中形成的第一阱，在衬底中形成的第二阱以及形成在第二阱中的第一掺杂区，其中， 第一阱，第二阱和第一掺杂区域共同形成寄生双极结型晶体管（BJT），其中第一阱是BJT的集电极，第二阱是BJT的基极，第一掺杂区域 是BJT的发射器。

公开(公告)号：US20070138589A1

公开(公告)日：2007-06-21

申请号：US11618685

申请日：2006-12-29

申请人： Yu-Da Shiu ,  Chyh-Yih Chang ,  Ming-Dou Ker ,  Che-Hao Chuang

发明人： Yu-Da Shiu ,  Chyh-Yih Chang ,  Ming-Dou Ker ,  Che-Hao Chuang

IPC分类号： H01L31/06

CPC分类号： H01L31/103 ,  H01L27/14609 ,  H01L31/105

摘要： An integrated circuit device for converting an incident optical signal into an electrical signal comprises a semiconductor substrate, a well region formed inside the semiconductor substrate, a dielectric layer formed over the well region, and a layer of polysilicon for receiving the incident optical signal, formed over the dielectric layer, including a p-type portion, an n-type portion and an undoped portion disposed between the p-type and n-type portions, wherein the well region is biased to control the layer of polysilicon for providing the electrical signal.

摘要翻译： 用于将入射光信号转换成电信号的集成电路装置包括半导体衬底，形成在半导体衬底内部的阱区，形成在阱区上的电介质层和用于接收入射光信号的多晶硅层，形成 包括p型部分，n型部分和设置在p型和n型部分之间的未掺杂部分，其中阱区被偏置以控制多晶硅层以提供电信号 。