公开(公告)号：US06590262B2

公开(公告)日：2003-07-08

申请号：US10082729

申请日：2002-02-26

Applicant: Jyh-Min Jiang ,  Kuo-Chio Liu ,  Jian-Hsing Lee ,  Ruey-Hsin Liu

Inventor： Jyh-Min Jiang ,  Kuo-Chio Liu ,  Jian-Hsing Lee ,  Ruey-Hsin Liu

IPC: H01L2701

CPC classification number: H01L27/0266 ,  H01L27/0288 ,  H01L29/7436 ,  H01L29/87

Abstract: A device layout is disclosed for an ESD device for protecting NMOS high voltage transistors where the SCR protection device and the two NMOS transistors are integrated. The two NMOS transistors share an n-type doped drain (ndd) area which has implanted two n+ drains, one for each of the two transistors and a p+ diffusion separates the two n+ drains. Furthermore, the ndd area has implanted an n-well which extends from halfway under the first n+ drain to halfway under the second n+ drain. In addition, the depth of the n-well exceeds the depth of the ndd area. The added p+ diffusion together with the ndd area and the p-substrate of the silicon wafer create the parasitic pnp transistors of the SCR. The shared ndd area together with the n+ sources of the NMOS transistors creates the SCR's two parasitic npn transistors. The low triggering voltage of the SCR is achieved by the combination of the n-well, the ndd area, the p+diffusion between the two drains, and by having the two parasitic npn transistors paralleled.

Abstract translation: 公开了用于保护NMOS高压晶体管的ESD器件的器件布局，其中SCR保护器件和两个NMOS晶体管被集成。 两个NMOS晶体管共享一个n型掺杂漏极（ndd）区域，其已经注入了两个n +漏极，一个用于两个晶体管中的每一个，p +扩散分离两个n +漏极。 此外，ndd区域已经注入n阱，其从第n +漏极下方的中途延伸到第二n +漏极下方的中间。 另外，n阱的深度超过ndd区域的深度。 添加的p +扩散与硅晶片的ndd区和p基底一起产生SCR的寄生pnp晶体管。 共享的ndd区域与NMOS晶体管的n +源产生SCR两个寄生npn晶体管。 SCR的低触发电压通过n阱，ndd面积，两个漏极之间的p +扩散以及两个寄生npn晶体管并联的组合来实现。

公开(公告)号：US06582997B1

公开(公告)日：2003-06-24

申请号：US10150833

申请日：2002-05-17

Applicant: Jian-Hsing Lee ,  Shui-Hun Chen ,  Jiaw-Ren Shih

Inventor： Jian-Hsing Lee ,  Shui-Hun Chen ,  Jiaw-Ren Shih

IPC: H01L218238

CPC classification number: H01L27/0266

Abstract: Disclosed are structures and a method to increase the power dissipation of an output pad of an integrated circuit during electrostatic discharge (ESD) by preventing ESD current from flowing through resistive means between that output pad and an internal circuit. By splitting the active region and thereby creating a bipolar transistor which connects directly to the output pad, the resistive means is shunted when the bipolar transistor together with an already existing parasitic bipolar transistor conduct during ESD. Current flow in the resistive means is therefore eliminated and with it damaging power dissipation.

公开(公告)号：US06455887B1

公开(公告)日：2002-09-24

申请号：US09320754

申请日：1999-05-27

Applicant: Yai-Fen Lin ,  Shiou-Hann Liaw ,  Di-Son Kuo ,  Jian-Hsing Lee

Inventor： Yai-Fen Lin ,  Shiou-Hann Liaw ,  Di-Son Kuo ,  Jian-Hsing Lee

IPC: H01L29788

CPC classification number: H01L27/11521 ,  G11C16/0441 ,  G11C16/045 ,  H01L27/115 ,  H01L29/7885

Abstract: An FET semiconductor device includes an N-region and a P-region formed in the substrate with the N-region juxtaposed with the P-region with an interface between the N-region and the P-region and with a first channel in the N-region and a second channel in the P-region. An N+ drain region is near the interface on one side of the first channel in the P-region. A P+ drain region is near the interface on one side of the second channel in the N-region. An N+ source region is on the opposite side of the first channel from the interface in the P-region. A P+ source region is on the opposite side of the first channel from the interface in the N-region. A wide gate electrode EEPROM stack bridges the channels in the N-region and the P-region. The stack includes a tunnel oxide layer, a floating gate electrode layer, an interelectrode dielectric layer, and a control gate electrode. An N+ drain region is formed in the surface of the P-region self-aligned with the gate electrode stack. A P+ drain region is formed in the surface of the N-region self-aligned with the gate electrode stack.

Abstract translation: FET半导体器件包括形成在衬底中的N区和P区，其中N区与P区并置，具有N区和P区之​​间的界面，并且N区中的第一通道 - 区域和P区域中的第二个通道。 N +漏极区域位于P区域中第一通道一侧的界面附近。 P +漏极区域位于N区域中第二通道一侧的界面附近。 N +源极区域与第一通道的与P区域中的界面相反。 P +源极区域与N区域中的界面在第一通道的相对侧。 宽栅电极EEPROM堆叠桥接N区和P区中的沟道。 堆叠包括隧道氧化物层，浮栅电极层，电极间电介质层和控制栅电极。 在与栅电极堆叠自对准的P区的表面中形成N +漏极区。 在与栅极电极堆叠自对准的N区域的表面中形成P +漏极区域。

公开(公告)号：US06444511B1

公开(公告)日：2002-09-03

申请号：US09867562

申请日：2001-05-31

Applicant: Yi-Hsu Wu ,  Hung-Der Su ,  Jian-Hsing Lee ,  Boon-Khim Liew

Inventor： Yi-Hsu Wu ,  Hung-Der Su ,  Jian-Hsing Lee ,  Boon-Khim Liew

IPC: H01L218238

CPC classification number: H01L27/092 ,  H01L21/823814 ,  H01L27/0266

Abstract: A new cascaded NMOS transistor output circuit with enhanced ESD protection is achieved. A driver PMOS transistor has the source connected to a voltage supply, the gate connected to the input signal, and the drain connected to the output pad. A dummy PMOS transistor has the source and the gate connected to the voltage supply, and the drain connected to the output pad. A driver NMOS cascaded stack comprises first and second NMOS transistors. The first NMOS transistor has the source connected to ground and the gate connected to the input signal. The second NMOS transistor has the gate connected to the voltage supply, the source connected to the first NMOS transistor drain, and the drain connected to the output pad. A p− implanted region underlies the n+ region of the drain but does not underlie the n+ region of the source. A dummy NMOS cascaded stack comprises third and fourth NMOS transistors. The third NMOS transistor has the gate and the source connected to ground. The fourth NMOS transistor has the gate connected to the voltage supply, the source connected to the third MOS transistor drain, and the drain connected to the output pad. A p− implanted region underlies the n+ region of the drain but does not underlie the n+ region of the source.

Abstract translation: 实现了具有增强ESD保护的新型级联NMOS晶体管输出电路。 驱动器PMOS晶体管的源极连接到电源，栅极连接到输入信号，漏极连接到输出焊盘。 虚设PMOS晶体管的源极和栅极连接到电源，漏极连接到输出焊盘。 驱动器NMOS级联堆叠包括第一和第二NMOS晶体管。 第一个NMOS晶体管的源极连接到地，栅极连接到输入信号。 第二个NMOS晶体管的栅极连接到电源，源极连接到第一个NMOS晶体管漏极，漏极连接到输出焊盘。 p-注入区域位于漏极的n +区域的下面，但不在源极的n +区域的下面。 虚设NMOS级联堆叠包括第三和第四NMOS晶体管。 第三个NMOS晶体管的栅极和源极接地。 第四个NMOS晶体管的栅极连接到电源，源极连接到第三个MOS晶体管漏极，漏极连接到输出焊盘。 p-注入区域位于漏极的n +区域的下面，但不在源极的n +区域的下面。

公开(公告)号：US06426855B2

公开(公告)日：2002-07-30

申请号：US09882685

申请日：2001-06-18

Applicant: Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Yi-Hsun Wu ,  Jing-Meng Liu

Inventor： Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Yi-Hsun Wu ,  Jing-Meng Liu

IPC: H02H900

CPC classification number: H01L27/0259

Abstract: A voltage clamping circuit that protects integrated circuits having multiple separate power supply voltage terminals from damage when an ESD event causes excessive differential voltages between the multiple separate power supply voltage terminals. The voltage clamping circuit has two subgroups of Darlington connected clamping transistors. The first subgroup of Darlington connected clamping transistors is connected between the first power supply voltage terminal and the second power supply voltage terminal. If the differential voltage exceeds the first clamping voltage level, the first subgroup of Darlington connected clamping transistors turn on and restore the first differential voltage to a level less than the first clamping voltage level. The second subgroup of Darlington connected clamping transistors connected between the second power supply terminal and the first power supply terminal. If the differential voltage exceeds the second clamping voltage level, the second subgroup of Darlington connected transistors turn on and restore the differential voltage to a level less than the second clamping voltage level.

公开(公告)号：US06323074B1

公开(公告)日：2001-11-27

申请号：US09557394

申请日：2000-04-24

Applicant: Jyh-Min Jiang ,  Kuo-Chio Liu ,  Jian-Hsing Lee ,  Ruey-Hsin Liu

Inventor： Jyh-Min Jiang ,  Kuo-Chio Liu ,  Jian-Hsing Lee ,  Ruey-Hsin Liu

IPC: H01L218238

CPC classification number: H01L27/0266 ,  H01L27/0288 ,  H01L29/7436 ,  H01L29/87

Abstract: A device layout is disclosed for an ESD device for protecting NMOS high voltage transistors where the SCR protection device and the two NMOS transistors are integrated. The two NMOS transistors share an n-type doped drain (ndd) area which has implanted two n+ drains, one for each of the two transistors and a p+ diffusion separates the two n+ drains. Furthermore, the ndd area has implanted an n-well which extends from halfway under the first n+ drain to halfway under the second n+ drain. In addition, the depth of the n-well exceeds the depth of the ndd area. The added p+diffusion together with the ndd area and the p-substrate of the silicon wafer create the parasitic pnp transistors of the SCR. The shared ndd area together with the n+ sources of the NMOS transistors creates the SCR's two parasitic npn transistors. The low triggering voltage of the SCR is achieved by the combination of the n-well, the ndd area, the p+diffusion between the two drains, and by having the two parasitic npn transistors paralleled.

Abstract translation: 公开了用于保护NMOS高压晶体管的ESD器件的器件布局，其中SCR保护器件和两个NMOS晶体管被集成。 两个NMOS晶体管共享一个n型掺杂漏极（ndd）区域，其已经注入了两个n +漏极，一个用于两个晶体管中的每一个，p +扩散分离两个n +漏极。 此外，ndd区域已经注入n阱，其从第n +漏极下方的中途延伸到第二n +漏极下方的中间。 另外，n阱的深度超过ndd区域的深度。 添加的p +扩散与硅晶片的ndd区和p基底一起产生SCR的寄生pnp晶体管。 共享的ndd区域与NMOS晶体管的n +源产生SCR两个寄生npn晶体管。 SCR的低触发电压通过n阱，ndd面积，两个漏极之间的p +扩散以及两个寄生npn晶体管并联的组合来实现。

公开(公告)号：US06303454B1

公开(公告)日：2001-10-16

申请号：US09590849

申请日：2000-06-09

Applicant: Juang-Ker Yeh ,  Jian-Hsing Lee ,  Kuo-Reay Peng ,  Ming-Chou Ho

Inventor： Juang-Ker Yeh ,  Jian-Hsing Lee ,  Kuo-Reay Peng ,  Ming-Chou Ho

IPC: H01L21336

CPC classification number: H01L29/66825 ,  G11C16/14 ,  H01L21/28273 ,  H01L29/7885

Abstract: The present invention provides method to fabricate a snap-back flash EEPROMS device. The method begins by forming a gate structure 22 24 28 26 on a substrate. The gate structure comprises: a tunnel oxide layer 22, a floating gate 24, integrate dielectric layer 28, and a control gate 26. A drain 14 is formed adjacent to the gate structure by an masking 51 and ion implant process. Next, a source side doped region 18 is formed adjacent to and under a portion of the gate structure 22 24 28 26 by an masking and ion implant process. Spacers 32 are now formed on the sidewalls of the gate structure. A source 20 is formed overlapping portion of the side source doped region 18 and adjacent to the spacers 32. The side source doped region has a lower dopant concentration than the source 20. This method forms a snap-back memory cell wherein the side source doped region 18 is used to apply a high voltage to operate the EEPROM cell in a snap-back erase mode.

Abstract translation: 本发明提供了制造快速闪存EEPROMS设备的方法。 该方法开始于在衬底上形成栅极结构22 24 28 26。 栅极结构包括：隧道氧化物层22，浮置栅极24，整合电介质层28和控制栅极26.漏极14通过掩模51和离子注入工艺邻近栅极结构形成。 接下来，通过掩模和离子注入工艺在栅极结构22 24 28 26的一部分附近形成源极侧掺杂区18。 隔板32现在形成在栅极结构的侧壁上。 源极20形成在侧面源极掺杂区域18的重叠部分并且与间隔物32相邻。源极掺杂区域具有比源极20更低的掺杂剂浓度。该方法形成一个回写式存储器单元，其中侧面源掺杂 区域18用于施加高电压以快速擦除模式操作EEPROM单元。

公开(公告)号：US06271999B1

公开(公告)日：2001-08-07

申请号：US09196603

申请日：1998-11-20

Applicant: Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Yi-Hsun Wu ,  Jing-Meng Liu

Inventor： Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Yi-Hsun Wu ,  Jing-Meng Liu

IPC: H02H900

CPC classification number: H01L27/0259

Abstract: A voltage clamping circuit that protects integrated circuits having multiple separate power supply voltage terminals from damage when an ESD event causes excessive differential voltages between the multiple separate power supply voltage terminals. The voltage clamping circuit has two subgroups of Darlington connected clamping transistors. The first subgroup of Darlington connected clamping transistors is connected between the first power supply voltage terminal and the second power supply voltage terminal. If the differential voltage exceeds the first clamping voltage level, the first subgroup of Darlington connected clamping transistors turn on and restore the first differential voltage to a level less than the first clamping voltage level. The second subgroup of Darlington connected clamping transistors connected between the second power supply terminal and the first power supply terminal. If the differential voltage exceeds the second clamping voltage level, the second subgroup of Darlington connected transistors turn on and restore the differential voltage to a level less than the second clamping voltage level.

Abstract translation: 一种电压钳位电路，当ESD事件在多个分离的电源电压端子之间引起过大的差分电压时，保护具有多个单独的电源电压端子的集成电路免受损坏。 电压钳位电路有两个Darlington连接钳位晶体管的子组。 达林顿连接的钳位晶体管的第一个子组连接在第一电源电压端子和第二电源电压端子之间。 如果差分电压超过第一钳位电压电平，则达林顿连接的钳位晶体管的第一个子组导通，并将第一个差分电压恢复到小于第一钳位电压电平的电平。 连接在第二电源端子和第一电源端子之间的达林顿的第二子组连接钳位晶体管。 如果差分电压超过第二钳位电压电平，则达林顿连接晶体管的第二个子组导通，并将差分电压恢复到小于第二钳位电压电平的电平。

公开(公告)号：US06249414B1

公开(公告)日：2001-06-19

申请号：US09670404

申请日：2000-09-28

Applicant: Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Yi-Hsun Wu ,  Jing-Meng Liu

Inventor： Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Yi-Hsun Wu ,  Jing-Meng Liu

IPC: H02H322

CPC classification number: H01L27/0262 ,  H01L29/87

Abstract: Circuits, device structures and methods are disclosed which protect CMOS semiconductor devices, having oxides as thin as 32 Angstrom, from electrostatic discharge (ESD) by utilizing a parasitic silicon controlled rectifier (SCR), intrinsic to the semiconductor device. The protection is afforded by providing low voltage triggering of the parasitic SCR in the order of 1.2 Volt. Triggering at such low voltages is made possible by means of a displacement current trigger which causes components of the SCR (parasitic npn and pnp bipolar transistors) to conduct, i.e., to trigger the SCR. The displacement current is realized by a junction capacitance, which is connected on one side to the pad to be protected and on the other side to terminals of the aforementioned parasitic bipolar transistors. Two ways of realizing the junction capacitance are disclosed.

Abstract translation: 公开了电路，器件结构和方法，其通过利用半导体器件固有的寄生可控硅整流器（SCR）来保护具有薄至32埃的氧化物的CMOS半导体器件免受静电放电（ESD）的影响。 通过提供大约1.2伏的寄生SCR的低电压触发来提供保护。 借助于使SCR（寄生npn和pnp双极型晶体管）的分量导通（即触发SCR）的位移电流触发，可以在这样的低电压下进行触发。 位移电流由结电容实现，该结电容器在一侧连接到待保护的焊盘，另一侧连接到上述寄生双极晶体管的端子。 公开了实现结电容的两种方式。

公开(公告)号：US06214670B1

公开(公告)日：2001-04-10

申请号：US09358986

申请日：1999-07-22

Applicant: Jiaw-Ren Shih ,  Shui-Hung Chen ,  Jian-Hsing Lee

Inventor： Jiaw-Ren Shih ,  Shui-Hung Chen ,  Jian-Hsing Lee

IPC: H01L21336

CPC classification number: H01L29/66613 ,  H01L29/7834

Abstract: In short-channel MOSFET devices with gates constructed using conventional double-diffusing techniques, damage to the silicon substrate region near the gate structure causes hot carrier effects that degrade the device performance. The inventive process described minimizes damage to the silicon substrate in the region of the metal gate structure thereby providing a MOSFET device with superior hot carrier effect performance.

Abstract translation: 在采用常规双重扩散技术构造的栅极的短沟道MOSFET器件中，栅极结构附近的硅衬底区域的损坏会导致热载流子效应降低器件性能。 所描述的本发明方法使得在金属栅极结构的区域中对硅衬底的损坏最小化，从而提供具有优异热载流子效应性能的MOSFET器件。