公开(公告)号：US10038054B2

公开(公告)日：2018-07-31

申请号：US15429126

申请日：2017-02-09

申请人： Intel Corporation

发明人： Willy Rachmady ,  Van H. Le ,  Ravi Pillarisetty ,  Jack T. Kavalieros ,  Robert S. Chau ,  Seung Hoon Sung

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/417 ,  H01L21/306

CPC分类号： H01L29/0676 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02603 ,  H01L21/30604 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66613 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78696 ,  H01L2029/7858 ,  Y10S977/762 ,  Y10S977/89 ,  Y10S977/938

摘要： Nanowire-based gate all-around transistor devices having one or more active nanowires and one or more inactive nanowires are described herein. Methods to fabricate such devices are also described. One or more embodiments of the present invention are directed at approaches for varying the gate width of a transistor structure comprising a nanowire stack having a distinct number of nanowires. The approaches include rendering a certain number of nanowires inactive (i.e. so that current does not flow through the nanowire), by severing the channel region, burying the source and drain regions, or both. Overall, the gate width of nanowire-based structures having a plurality of nanowires may be varied by rendering a certain number of nanowires inactive, while maintaining other nanowires as active.

公开(公告)号：US20180114858A1

公开(公告)日：2018-04-26

申请号：US15631820

申请日：2017-06-23

申请人： United Microelectronics Corp.

发明人： Cheng-Hsun Chung ,  Shih-Teng Huang ,  Tien-Shang Kuo

IPC分类号： H01L29/78 ,  H01L29/49 ,  H01L29/51 ,  H01L29/36 ,  H01L23/535 ,  H01L21/768 ,  H01L21/285

CPC分类号： H01L29/7816 ,  H01L21/285 ,  H01L21/76895 ,  H01L23/535 ,  H01L29/36 ,  H01L29/402 ,  H01L29/4983 ,  H01L29/512 ,  H01L29/66613 ,  H01L29/66681 ,  H01L29/7824

摘要： A transistor structure including a gate, a first dielectric layer, a first contact and a second contact is provided. The gate is disposed on a substrate. The first dielectric layer is disposed on the substrate. The first dielectric layer covers a portion of a top surface of the gate. The first contact is electrically connected to the gate. The second contact is disposed on the first dielectric layer. The second contact is electrically connected with the first contact.

公开(公告)号：US20180076294A1

公开(公告)日：2018-03-15

申请号：US15726026

申请日：2017-10-05

申请人： ROHM CO., LTD.

发明人： Yuki NAKANO

IPC分类号： H01L29/423 ,  H01L29/66 ,  H01L29/40 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L29/4236 ,  H01L29/0615 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/407 ,  H01L29/66045 ,  H01L29/66068 ,  H01L29/66613 ,  H01L29/66734 ,  H01L29/78 ,  H01L29/7811 ,  H01L29/7813

摘要： A semiconductor device of the present invention includes a gate electrode buried in a gate trench of a first conductivity-type semiconductor layer, a first conductivity-type source region, a second conductivity-type channel region, and a first conductivity-type drain region formed in the semiconductor layer, a second trench selectively formed in a source portion defined in a manner containing the source region in the surface of the semiconductor layer, a trench buried portion buried in the second trench, a second conductivity-type channel contact region selectively disposed at a position higher than that of a bottom portion of the second trench in the source portion, and electrically connected with the channel region, and a surface metal layer disposed on the source portion, and electrically connected to the source region and the channel contact region.

公开(公告)号：US20180053858A1

公开(公告)日：2018-02-22

申请号：US15533336

申请日：2016-05-09

申请人： BOE TECHNOLOGY GROUP CO., LTD.

发明人： Hui Tian

IPC分类号： H01L29/786 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49

CPC分类号： H01L29/78603 ,  H01L21/28 ,  H01L21/283 ,  H01L29/40 ,  H01L29/423 ,  H01L29/4908 ,  H01L29/51 ,  H01L29/66477 ,  H01L29/66613 ,  H01L29/66742 ,  H01L29/66757 ,  H01L29/78 ,  H01L29/786

摘要： The present disclosure relates to a thin film transistor and a method of manufacturing the same, and a display device. The thin film transistor comprises a substrate, and, a source electrode, a drain electrode, a gate, a gate insulation layer and an active layer disposed on the substrate; the gate insulation layer is located between the gate and the active layer, and the source electrode and the drain electrode are connected to the active layer, respectively; and the gate is a composite metal layer comprising at least one first metal layer which contains doped ions therein and which is close to the gate insulation layer, and at least one second metal layer which is apart from the gate insulation layer.

公开(公告)号：US20180026102A1

公开(公告)日：2018-01-25

申请号：US15547682

申请日：2015-02-18

申请人： The University of Warwick

发明人： Peter Gammon ,  Chun Wa Chan

IPC分类号： H01L29/16 ,  H01L29/739 ,  H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66

CPC分类号： H01L29/66681 ,  H01L21/7602 ,  H01L21/76202 ,  H01L21/7624 ,  H01L29/063 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66613 ,  H01L29/7393 ,  H01L29/7816 ,  H01L29/7835

摘要： A power semiconductor device is described. The device comprises a silicon carbide substrate and a layer of monocrystalline silicon having a thickness tSi no more than 5 μm disposed directly on the substrate or directly on an interfacial layer having a thickness no more than 100 nm which is disposed directly on the substrate. The device comprises a lateral transistor, such as a laterally-diffused metal oxide semiconductor transistor or lateral insulated gate bipolar transistor, comprising first and second contacts laterally-spaced contact regions disposed in the monocrystalline silicon layer.

公开(公告)号：US09741808B2

公开(公告)日：2017-08-22

申请号：US15061912

申请日：2016-03-04

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Yeeheng Lee ,  Lingpeng Guan ,  Hongyong Xue ,  Yiming Gu ,  Yang Xiang ,  Terence Huang ,  Sekar Ramamoorthy ,  Wenjun Li ,  Hong Chang ,  Madhur Bobde ,  Paul Thorup ,  Hamza Yilmaz

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/40 ,  H01L27/088

CPC分类号： H01L29/4236 ,  H01L21/28008 ,  H01L27/088 ,  H01L29/404 ,  H01L29/407 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66484 ,  H01L29/66613 ,  H01L29/66734 ,  H01L29/78 ,  H01L29/7811 ,  H01L29/7813

摘要： A plurality of gate trenches is formed into a semiconductor substrate in an active cell region. One or more other trenches are formed in a different region. Each gate trench has a first conductive material in lower portions and a second conductive material in upper portions. In the gate trenches, a first insulating layer separates the first conductive material from the substrate, a second insulating layer separates the second conductive material from the substrate and a third insulating material separates the first and second conductive materials. The other trenches contain part of the first conductive material in a half-U shape in lower portions and part of the second conductive material in upper portions. In the other trenches, the third insulating layer separates the first and second conductive materials. The first insulating layer is thicker than the third insulating layer, and the third insulating layer is thicker than the second.

公开(公告)号：US20160308028A1

公开(公告)日：2016-10-20

申请号：US15187232

申请日：2016-06-20

申请人： Infineon Technologies Austria AG

发明人： Ravi Joshi ,  Johannes Baumgartl ,  Martin Poelzl ,  Matthias Kuenle ,  Juergen Steinbrenner ,  Andreas Haghofer ,  Christoph Gruber ,  Georg Ehrentraut

IPC分类号： H01L29/66 ,  H01L29/423 ,  H01L21/311 ,  H01L21/02 ,  H01L21/306

CPC分类号： H01L29/66613 ,  H01L21/02233 ,  H01L21/02647 ,  H01L21/30604 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/0649 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/78 ,  H01L29/7813 ,  H01L29/7827

摘要： In one aspect, a method of forming a trench in a semiconductor material includes forming a first dielectric layer on a semiconductor substrate. The first dielectric layer includes first openings. An epitaxial layer is grown on the semiconductor substrate by an epitaxial lateral overgrowth process. The first openings are filled by the epitaxial layer and the epitaxial layer is grown onto adjacent portions of the first dielectric layer so that part of the first dielectric layer is uncovered by the epitaxial layer and a gap forms between opposing sidewalls of the epitaxial layer over the part of the first dielectric layer that is uncovered by the epitaxial layer. The gap defines a first trench in the epitaxial layer that extends to the first dielectric layer.

摘要翻译： 一方面，在半导体材料中形成沟槽的方法包括在半导体衬底上形成第一电介质层。 第一介电层包括第一开口。 通过外延横向过度生长工艺在半导体衬底上生长外延层。 第一开口由外延层填充，并且外延层生长到第一介电层的相邻部分上，使得第一介电层的一部分未被外延层覆盖，并且在外延层的相对侧壁之间形成间隙 由外延层未覆盖的第一电介质层的一部分。 该间隙限定外延层中延伸到第一介电层的第一沟槽。

公开(公告)号：US09449978B2

公开(公告)日：2016-09-20

申请号：US14148402

申请日：2014-01-06

申请人： Micron Technology, Inc.

发明人： Kamal M. Karda ,  Mingtao Li ,  Haitao Liu ,  Deepak Chandra Pandey ,  Mark Fischer

IPC分类号： H01L27/108 ,  H01L27/105 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L27/10879 ,  H01L27/1052 ,  H01L27/10891 ,  H01L29/66613 ,  H01L29/66818 ,  H01L29/785 ,  H01L2029/7857

摘要： A semiconductor device comprises a recessed access device that includes a first pillar, a second pillar, a channel region connecting the first and second pillars, and a gate disposed over the channel region. The channel region has a width that is narrower than widths of the first pillar and the second pillar. An array of recessed access devices comprises a plurality of pillars protruding from a substrate, and a plurality of channel regions. Each channel region has a width that is less than about 10 nm and couples neighboring pillars to form a plurality of junctionless recessed access devices. A method of forming at least one recessed access device also comprises forming pillars over a substrate, forming at least a channel region coupled with the pillars, the channel region having a relatively narrow width, and forming a gate at least partially surrounding the channel region on at least three sides.

摘要翻译： 一种半导体器件包括凹入的存取器件，其包括第一柱，第二柱，连接第一和第二柱的沟道区，以及设置在沟道区上的栅。 沟道区具有比第一柱和第二柱的宽度窄的宽度。 凹陷进入装置的阵列包括从基板突出的多个支柱和多个通道区域。 每个通道区域具有小于约10nm的宽度并且连接相邻的柱以形成多个无连接的凹入式接入设备。 一种形成至少一个凹陷进入装置的方法还包括在衬底上形成柱，形成至少与柱相连的沟道区，沟道区具有相对较窄的宽度，以及形成至少部分围绕沟道区的栅极 至少三面。

公开(公告)号：US20160268341A1

公开(公告)日：2016-09-15

申请号：US14795105

申请日：2015-07-09

申请人： Crossbar, Inc.

发明人： Hagop Nazarian ,  Sung Hyun Jo ,  Harry Yue Gee

IPC分类号： H01L27/24 ,  H01L29/66 ,  H01L45/00 ,  H01L29/423 ,  H01L49/02

CPC分类号： H01L27/2463 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C14/00 ,  G11C14/0045 ,  G11C2213/53 ,  G11C2213/79 ,  H01L27/2436 ,  H01L28/60 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/66613 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/148 ,  H01L45/1608

摘要： A high density non-volatile memory device is provided that uses one or more volatile elements. In some embodiments, the non-volatile memory device can include a resistive two-terminal selector that can be in a low resistive state or a high resistive state depending on the voltage being applied. A deep trench MOS (“metal-oxide-semiconductor”) transistor having a floating gate with small area relative to conventional devices can be provided, in addition to a capacitor or transistor acting as a capacitor. A first terminal of the capacitor can be connected to a voltage source, and the second terminal of the capacitor can be connected to the selector device. The small area floating gate of the deep trench transistor can be connected to the other side of the selector device, and a second transistor can be connected in series with the deep trench transistor.

摘要翻译： 提供了使用一个或多个易失性元件的高密度非易失性存储器件。 在一些实施例中，非易失性存储器件可以包括根据施加的电压可以处于低电阻状态或高电阻状态的电阻式两端选择器。 除了作为电容器的电容器或晶体管之外，还可以提供具有相对于常规器件具有小面积的浮动栅极的深沟槽MOS（“金属氧化物半导体”）晶体管。 电容器的第一端子可以连接到电压源，并且电容器的第二端子可以连接到选择器装置。 深沟槽晶体管的小面积浮栅可以连接到选择器件的另一侧，并且第二晶体管可以与深沟槽晶体管串联连接。

公开(公告)号：US20160240610A1

公开(公告)日：2016-08-18

申请号：US14620966

申请日：2015-02-12

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Joel P. de Souza ,  Keith E. Fogel ,  Jeehwan Kim ,  Devendra K. Sadana ,  Brent A. Wacaser

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/267

CPC分类号： H01L29/0847 ,  H01L29/0649 ,  H01L29/0895 ,  H01L29/267 ,  H01L29/66219 ,  H01L29/66522 ,  H01L29/66613 ,  H01L29/66643 ,  H01L29/66969 ,  H01L29/78 ,  H01L29/861 ,  H01L29/868

摘要： A semiconductor device includes a substrate and a p-doped layer including a doped III-V material on the substrate. A dielectric interlayer is formed on the p-doped layer. An n-type layer is formed on the dielectric interlayer, the n-type layer including a high band gap II-VI material to form an electronic device.

摘要翻译： 半导体器件包括衬底和在衬底上包括掺杂III-V材料的p掺杂层。 在p掺杂层上形成电介质中间层。 在电介质中间层上形成n型层，n型层包括高带隙II-VI材料以形成电子器件。